[llvm] r354197 - [X86] When type legalizing the result of a i64 fp_to_uint on 32-bit targets. Generate all of the ops as i64 and let them be legalized.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 16 00:25:42 PST 2019
Author: ctopper
Date: Sat Feb 16 00:25:42 2019
New Revision: 354197
URL: http://llvm.org/viewvc/llvm-project?rev=354197&view=rev
Log:
[X86] When type legalizing the result of a i64 fp_to_uint on 32-bit targets. Generate all of the ops as i64 and let them be legalized.
No need to manually split everything. We can let the type legalizer work for us.
The test change seems to be caused by some DAG ordering issue that was previously circumventing a one use check in LowerSELECT where FP selects are turned into blends if the setcc has one use. But it was running after an integer select and the same setcc had been legalized to cmov and X86SISD::CMP. This dropped the use count of the setcc, but wasn't what was intended.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/vec_cast3.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=354197&r1=354196&r2=354197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Feb 16 00:25:42 2019
@@ -18149,9 +18149,10 @@ X86TargetLowering::FP_TO_INTHelper(SDVal
getSetCCResultType(DAG.getDataLayout(),
*DAG.getContext(), TheVT),
Value, ThreshVal, ISD::SETLT);
- Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
- DAG.getConstant(0, DL, MVT::i32),
- DAG.getConstant(0x80000000, DL, MVT::i32));
+ Adjust = DAG.getSelect(DL, MVT::i64, Cmp,
+ DAG.getConstant(0, DL, MVT::i64),
+ DAG.getConstant(APInt::getSignMask(64),
+ DL, MVT::i64));
SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
*DAG.getContext(), TheVT),
@@ -18188,32 +18189,14 @@ X86TargetLowering::FP_TO_INTHelper(SDVal
DAG.getVTList(MVT::Other),
Ops, DstTy, MMO);
- if (!UnsignedFixup)
- return DAG.getLoad(Op.getValueType(), SDLoc(Op), FIST, StackSlot,
- MachinePointerInfo());
-
- // Insert the FIST, load its result as two i32's,
- // and XOR the high i32 with Adjust.
-
- SDValue Low32 =
- DAG.getLoad(MVT::i32, DL, FIST, StackSlot, MachinePointerInfo());
- SDValue HighAddr = DAG.getMemBasePlusOffset(StackSlot, 4, DL);
-
- SDValue High32 =
- DAG.getLoad(MVT::i32, DL, FIST, HighAddr, MachinePointerInfo());
- High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
-
- if (Subtarget.is64Bit()) {
- // Join High32 and Low32 into a 64-bit result.
- // (High32 << 32) | Low32
- Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
- High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
- High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
- DAG.getConstant(32, DL, MVT::i8));
- return DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
- }
+ SDValue Res = DAG.getLoad(Op.getValueType(), SDLoc(Op), FIST, StackSlot,
+ MachinePointerInfo());
+
+ // If we need an unsigned fixup, XOR the result with adjust.
+ if (UnsignedFixup)
+ Res = DAG.getNode(ISD::XOR, DL, MVT::i64, Res, Adjust);
- return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, { Low32, High32 });
+ return Res;
}
static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
Modified: llvm/trunk/test/CodeGen/X86/vec_cast3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_cast3.ll?rev=354197&r1=354196&r2=354197&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_cast3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_cast3.ll Sat Feb 16 00:25:42 2019
@@ -192,28 +192,30 @@ define <2 x i32> @cvt_v2f32_v2u32(<2 x f
; CHECK: ## %bb.0:
; CHECK-NEXT: subl $68, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 72
-; CHECK-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; CHECK-NEXT: vcmpltss %xmm2, %xmm1, %xmm3
-; CHECK-NEXT: vsubss %xmm2, %xmm1, %xmm4
-; CHECK-NEXT: vblendvps %xmm3, %xmm1, %xmm4, %xmm3
-; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
-; CHECK-NEXT: vcmpltss %xmm2, %xmm0, %xmm3
-; CHECK-NEXT: vsubss %xmm2, %xmm0, %xmm4
-; CHECK-NEXT: vblendvps %xmm3, %xmm0, %xmm4, %xmm3
-; CHECK-NEXT: vmovss %xmm3, {{[0-9]+}}(%esp)
+; CHECK-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: vucomiss %xmm1, %xmm2
+; CHECK-NEXT: jb LBB11_2
+; CHECK-NEXT: ## %bb.1:
+; CHECK-NEXT: vsubss %xmm1, %xmm2, %xmm2
+; CHECK-NEXT: LBB11_2:
+; CHECK-NEXT: vmovss %xmm2, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: fisttpll (%esp)
-; CHECK-NEXT: flds {{[0-9]+}}(%esp)
-; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: vucomiss %xmm2, %xmm1
; CHECK-NEXT: setae %al
+; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: shll $31, %eax
; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: vucomiss %xmm2, %xmm0
+; CHECK-NEXT: vucomiss %xmm1, %xmm0
+; CHECK-NEXT: jb LBB11_4
+; CHECK-NEXT: ## %bb.3:
+; CHECK-NEXT: vsubss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: LBB11_4:
+; CHECK-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT: flds {{[0-9]+}}(%esp)
+; CHECK-NEXT: fisttpll {{[0-9]+}}(%esp)
; CHECK-NEXT: setae %cl
+; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: shll $31, %ecx
; CHECK-NEXT: xorl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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