[llvm] r354150 - [MCA][LSUnit] Return the ID of the dependent memory operation from method
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 15 10:06:00 PST 2019
Author: adibiagio
Date: Fri Feb 15 10:05:59 2019
New Revision: 354150
URL: http://llvm.org/viewvc/llvm-project?rev=354150&view=rev
Log:
[MCA][LSUnit] Return the ID of the dependent memory operation from method
isReady(). NFCI
This is yet another change in preparation for a fix for PR37494.
Modified:
llvm/trunk/include/llvm/MCA/HardwareUnits/LSUnit.h
llvm/trunk/lib/MCA/HardwareUnits/LSUnit.cpp
llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
Modified: llvm/trunk/include/llvm/MCA/HardwareUnits/LSUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MCA/HardwareUnits/LSUnit.h?rev=354150&r1=354149&r2=354150&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MCA/HardwareUnits/LSUnit.h (original)
+++ llvm/trunk/include/llvm/MCA/HardwareUnits/LSUnit.h Fri Feb 15 10:05:59 2019
@@ -187,7 +187,11 @@ public:
// 4. A store may not pass a previous load (regardless of flag 'NoAlias').
// 5. A load has to wait until an older load barrier is fully executed.
// 6. A store has to wait until an older store barrier is fully executed.
- virtual bool isReady(const InstRef &IR) const;
+ //
+ // Returns an instruction identifier. If IR is ready, then this method returns
+ // `IR.getSourceIndex()`. Otherwise it returns the instruction ID of the
+ // dependent (i.e. conflicting) memory instruction.
+ virtual unsigned isReady(const InstRef &IR) const;
// Load and store instructions are tracked by their corresponding queues from
// dispatch until the "instruction executed" event.
Modified: llvm/trunk/lib/MCA/HardwareUnits/LSUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/HardwareUnits/LSUnit.cpp?rev=354150&r1=354149&r2=354150&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/HardwareUnits/LSUnit.cpp (original)
+++ llvm/trunk/lib/MCA/HardwareUnits/LSUnit.cpp Fri Feb 15 10:05:59 2019
@@ -93,7 +93,7 @@ LSUnit::Status LSUnit::isAvailable(const
return LSUnit::LSU_AVAILABLE;
}
-bool LSUnit::isReady(const InstRef &IR) const {
+unsigned LSUnit::isReady(const InstRef &IR) const {
const InstrDesc &Desc = IR.getInstruction()->getDesc();
const unsigned Index = IR.getSourceIndex();
bool IsALoad = Desc.MayLoad;
@@ -106,49 +106,52 @@ bool LSUnit::isReady(const InstRef &IR)
unsigned LoadBarrierIndex = *LoadBarriers.begin();
// A younger load cannot pass a older load barrier.
if (Index > LoadBarrierIndex)
- return false;
+ return LoadBarrierIndex;
// A load barrier cannot pass a older load.
if (Index == LoadBarrierIndex && Index != *LoadQueue.begin())
- return false;
+ return *LoadQueue.begin();
}
if (IsAStore && !StoreBarriers.empty()) {
unsigned StoreBarrierIndex = *StoreBarriers.begin();
// A younger store cannot pass a older store barrier.
if (Index > StoreBarrierIndex)
- return false;
+ return StoreBarrierIndex;
// A store barrier cannot pass a older store.
if (Index == StoreBarrierIndex && Index != *StoreQueue.begin())
- return false;
+ return *StoreQueue.begin();
}
// A load may not pass a previous store unless flag 'NoAlias' is set.
// A load may pass a previous load.
if (NoAlias && IsALoad)
- return true;
+ return Index;
if (StoreQueue.size()) {
// A load may not pass a previous store.
// A store may not pass a previous store.
if (Index > *StoreQueue.begin())
- return false;
+ return *StoreQueue.begin();
}
// Okay, we are older than the oldest store in the queue.
// If there are no pending loads, then we can say for sure that this
// instruction is ready.
if (isLQEmpty())
- return true;
+ return Index;
// Check if there are no older loads.
if (Index <= *LoadQueue.begin())
- return true;
+ return Index;
// There is at least one younger load.
//
- // A store may not pass a previous load.
// A load may pass a previous load.
- return !IsAStore;
+ if (IsALoad)
+ return Index;
+
+ // A store may not pass a previous load.
+ return *LoadQueue.begin();
}
void LSUnit::onInstructionExecuted(const InstRef &IR) {
Modified: llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp?rev=354150&r1=354149&r2=354150&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp (original)
+++ llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp Fri Feb 15 10:05:59 2019
@@ -288,7 +288,8 @@ void Scheduler::dispatch(const InstRef &
bool Scheduler::isReady(const InstRef &IR) const {
const InstrDesc &Desc = IR.getInstruction()->getDesc();
bool IsMemOp = Desc.MayLoad || Desc.MayStore;
- return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR));
+ return IR.getInstruction()->isReady() &&
+ (!IsMemOp || LSU.isReady(IR) == IR.getSourceIndex());
}
} // namespace mca
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