[PATCH] D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V

[Alex Bradbury via Phabricator via llvm-commits]

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Did you check the behaviour of 'J' vs GCC, because for e.g. `asm volatile ("sub a0, a0, %0" :: "J"(0));` I seem to see it using the integer 0 rather than the zero register?

I think it would be worth adding RV64I check lines to inline-asm.ll too.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D54093/new/

https://reviews.llvm.org/D54093