[PATCH] D55279: [RISCV] Support assembling %got_pcrel_hi operator

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.

Thanks, this looks good to me (see small nit in comment). Do you need me to commit?



================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:194
   case RISCV::fixup_riscv_pcrel_hi20:
+  case RISCV::fixup_riscv_got_hi20:
     // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
----------------
Given that we expect a relocation will always be emitted, perhaps we should add instead:

```

case RISCV::fixup_riscv_got_hi20:
  llvm_unreachable("Relocation should have been forced for fixup")
```


Repository:
  rL LLVM

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  https://reviews.llvm.org/D55279/new/

https://reviews.llvm.org/D55279