[PATCH] D57833: [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: lib/Target/ARM/ARMBaseInstrInfo.cpp:2659
+      (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8) &&
+      OI->getOperand(0).getReg() == SrcReg &&
+      OI->getOperand(2).getReg() == SrcReg2)
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efriedma wrote:
> The corresponding ARM/Thumb2 code checks for ADDrr; should we add the corresponding check for tADDrr? 
>  Or does that not work for some reason?
Thanks, that was lost in a reshuffle I think. It does show up some machine verifier problems with this. IsThumb1 isn't being set correctly


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57833/new/

https://reviews.llvm.org/D57833