[PATCH] D58068: [DAG] Avoid smart constructor-based dangling nodes.

[Nirav Dave via Phabricator via llvm-commits]

niravd created this revision.
niravd added reviewers: efriedma, RKSimon, craig.topper.
Herald added subscribers: jsji, atanasyan, jrtc27, hiraditya, javed.absar, nemanjai, sdardis.
Herald added a project: LLVM.

Various SelectionDAG non-combine operations (e.g. the getNode smart
constructor and legalization) may leave dangling nodes by applying
optimizations without fully pruning unused result values. This results
in nodes that are never added to the worklist and therefore can not be
pruned.

Add a node inserter for the combiner to make sure such nodes have the
chance of being pruned. This allows a number of additional peephole
optimizations.

Some regressions occur here, but are resolved by a followup patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D58068

Files:
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
  llvm/test/CodeGen/ARM/arm-storebytesmerge.ll
  llvm/test/CodeGen/ARM/vdup.ll
  llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
  llvm/test/CodeGen/X86/3addr-or.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/sat-add.ll
  llvm/test/CodeGen/X86/select_const.ll
  llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
  llvm/test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll
  llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
  llvm/test/CodeGen/X86/uadd_sat_vec.ll
  llvm/test/CodeGen/X86/umul_fix.ll
  llvm/test/CodeGen/X86/usub_sat_vec.ll
  llvm/test/CodeGen/X86/vec_minmax_sint.ll
  llvm/test/CodeGen/X86/vec_minmax_uint.ll
  llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-smin.ll
  llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
  llvm/test/CodeGen/X86/vector-trunc-packus-widen.ll
  llvm/test/CodeGen/X86/vector-trunc-packus.ll
  llvm/test/CodeGen/X86/vector-trunc-ssat-widen.ll
  llvm/test/CodeGen/X86/vector-trunc-ssat.ll
  llvm/test/CodeGen/X86/vector-trunc-usat-widen.ll
  llvm/test/CodeGen/X86/vector-trunc-usat.ll
  llvm/test/CodeGen/X86/vsel-cmp-load.ll
  llvm/test/CodeGen/X86/xor.ll
  llvm/test/CodeGen/X86/zext-demanded.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

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