[llvm] r353722 - [GlobalISel][AArch64] Select G_FFLOOR
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 11 09:22:58 PST 2019
Author: paquette
Date: Mon Feb 11 09:22:58 2019
New Revision: 353722
URL: http://llvm.org/viewvc/llvm-project?rev=353722&view=rev
Log:
[GlobalISel][AArch64] Select G_FFLOOR
This teaches the legalizer about G_FFLOOR, and lets us select G_FFLOOR in
AArch64.
It updates the existing floating point tests, and adds a select-floor.mir test.
Differential Revision: https://reviews.llvm.org/D57486
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-floor.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=353722&r1=353721&r2=353722&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Mon Feb 11 09:22:58 2019
@@ -1358,6 +1358,7 @@ LegalizerHelper::widenScalar(MachineInst
case TargetOpcode::G_FDIV:
case TargetOpcode::G_FREM:
case TargetOpcode::G_FCEIL:
+ case TargetOpcode::G_FFLOOR:
case TargetOpcode::G_FCOS:
case TargetOpcode::G_FSIN:
case TargetOpcode::G_FLOG10:
@@ -2147,6 +2148,7 @@ LegalizerHelper::fewerElementsVector(Mac
case G_FLOG2:
case G_FLOG10:
case G_FCEIL:
+ case G_FFLOOR:
case G_INTRINSIC_ROUND:
case G_INTRINSIC_TRUNC:
case G_FCOS:
Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=353722&r1=353721&r2=353722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Mon Feb 11 09:22:58 2019
@@ -126,7 +126,7 @@ AArch64LegalizerInfo::AArch64LegalizerIn
getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
- getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT})
+ getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
.fewerElementsIf(
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=353722&r1=353721&r2=353722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Mon Feb 11 09:22:58 2019
@@ -392,6 +392,7 @@ static bool isPreISelGenericFloatingPoin
case TargetOpcode::G_FPEXT:
case TargetOpcode::G_FPTRUNC:
case TargetOpcode::G_FCEIL:
+ case TargetOpcode::G_FFLOOR:
case TargetOpcode::G_FNEG:
case TargetOpcode::G_FCOS:
case TargetOpcode::G_FSIN:
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-floor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-floor.mir?rev=353722&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-floor.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-floor.mir Mon Feb 11 09:22:58 2019
@@ -0,0 +1,130 @@
+# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
+# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
+# RUN: | FileCheck %s
+...
+---
+name: floor_float
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_float
+ ; CHECK: %{{[0-9]+}}:fpr32 = FRINTMSr %{{[0-9]+}}
+ liveins: $s0
+ %0:fpr(s32) = COPY $s0
+ %1:fpr(s32) = G_FFLOOR %0
+ $s0 = COPY %1(s32)
+
+...
+---
+name: floor_double
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_double
+ ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMDr %{{[0-9]+}}
+ liveins: $d0
+ %0:fpr(s64) = COPY $d0
+ %1:fpr(s64) = G_FFLOOR %0
+ $d0 = COPY %1(s64)
+
+...
+---
+name: floor_v2f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_v2f32
+ ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv2f32 %{{[0-9]+}}
+ liveins: $d0
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s32>) = G_FFLOOR %0
+ $d0 = COPY %1(<2 x s32>)
+
+...
+---
+name: floor_v4f32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_v4f32
+ ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv4f32 %{{[0-9]+}}
+ liveins: $q0
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:fpr(<4 x s32>) = G_FFLOOR %0
+ $q0 = COPY %1(<4 x s32>)
+
+...
+---
+name: floor_v2f64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_v2f64
+ ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv2f64 %{{[0-9]+}}
+ liveins: $q0
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s64>) = G_FFLOOR %0
+ $q0 = COPY %1(<2 x s64>)
+
+...
+---
+name: floor_v4f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_v4f16
+ ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv4f16 %{{[0-9]+}}
+ liveins: $d0
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s16>) = G_FFLOOR %0
+ $d0 = COPY %1(<4 x s16>)
+
+...
+---
+name: floor_v8f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr }
+ - { id: 1, class: fpr }
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: floor_v8f16
+ ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv8f16 %{{[0-9]+}}
+ liveins: $q0
+ %0:fpr(<8 x s16>) = COPY $q0
+ %1:fpr(<8 x s16>) = G_FFLOOR %0
+ $q0 = COPY %1(<8 x s16>)
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll?rev=353722&r1=353721&r2=353722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll Mon Feb 11 09:22:58 2019
@@ -141,12 +141,20 @@ define %v4f16 @test_v4f16.fabs(%v4f16 %a
%1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
ret %v4f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v4f16.floor
define %v4f16 @test_v4f16.floor(%v4f16 %a) {
; CHECK-LABEL: test_v4f16.floor:
; CHECK-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frintm.4h
; CHECK-FP16-NEXT: ret
+
+ ; GISEL-LABEL: test_v4f16.floor:
+ ; GISEL-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frintm.4h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v4f16 @llvm.floor.v4f16(%v4f16 %a)
ret %v4f16 %1
}
@@ -342,12 +350,20 @@ define %v8f16 @test_v8f16.fabs(%v8f16 %a
%1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a)
ret %v8f16 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v8f16.floor
define %v8f16 @test_v8f16.floor(%v8f16 %a) {
; CHECK-LABEL: test_v8f16.floor:
; CHECK-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}}
; CHECK-FP16-NOT: fcvt
; CHECK-FP16: frintm.8h
; CHECK-FP16-NEXT: ret
+
+ ; GISEL-LABEL: test_v8f16.floor:
+ ; GISEL-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}}
+ ; GISEL-FP16-NOT: fcvt
+ ; GISEL-FP16: frintm.8h
+ ; GISEL-FP16-NEXT: ret
%1 = call %v8f16 @llvm.floor.v8f16(%v8f16 %a)
ret %v8f16 %1
}
@@ -516,9 +532,13 @@ define %v2f32 @test_v2f32.fabs(%v2f32 %a
%1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
ret %v2f32 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v2f32.floor
; CHECK-LABEL: test_v2f32.floor:
+; GISEL-LABEL: test_v2f32.floor:
define %v2f32 @test_v2f32.floor(%v2f32 %a) {
; CHECK: frintm.2s
+ ; GISEL: frintm.2s
%1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
ret %v2f32 %1
}
@@ -671,9 +691,13 @@ define %v4f32 @test_v4f32.fabs(%v4f32 %a
%1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a)
ret %v4f32 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v4f32.floor
; CHECK: test_v4f32.floor:
+; GISEL: test_v4f32.floor:
define %v4f32 @test_v4f32.floor(%v4f32 %a) {
; CHECK: frintm.4s
+ ; GISEL frintm.4s
%1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
ret %v4f32 %1
}
@@ -826,9 +850,13 @@ define %v2f64 @test_v2f64.fabs(%v2f64 %a
%1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
ret %v2f64 %1
}
+
+; FALLBACK-NOT: remark{{.*}}test_v2f64.floor
; CHECK: test_v2f64.floor:
+; GISEL: test_v2f64.floor:
define %v2f64 @test_v2f64.floor(%v2f64 %a) {
; CHECK: frintm.2d
+ ; GISEL: frintm.2d
%1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a)
ret %v2f64 %1
}
Modified: llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=353722&r1=353721&r2=353722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll Mon Feb 11 09:22:58 2019
@@ -1168,6 +1168,19 @@ define float @test_copysign_extended(hal
; CHECK-FP16-NEXT: frintm h0, h0
; CHECK-FP16-NEXT: ret
+; FALLBACK-NOT: remark:{{.*}}test_floor
+; FALLBACK-FP16-NOT: remark:{{.*}}test_floor
+
+; GISEL-CVT-LABEL: test_floor:
+; GISEL-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
+; GISEL-CVT-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]]
+; GISEL-CVT-NEXT: fcvt h0, [[INT32]]
+; GISEL-CVT-NEXT: ret
+
+; GISEL-FP16-LABEL: test_floor:
+; GISEL-FP16-NEXT: frintm h0, h0
+; GISEL-FP16-NEXT: ret
+
define half @test_floor(half %a) #0 {
%r = call half @llvm.floor.f16(half %a)
ret half %r
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