[PATCH] D45355: [SelectionDAG] Fix return calling convention in expansion of ?MULO

[whitequark via Phabricator via llvm-commits]

whitequark updated this revision to Diff 186274.
whitequark added a comment.
Herald added a project: LLVM.

Added a test, based on the one provided by @george-hopkins but modified to pass on master.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D45355/new/

https://reviews.llvm.org/D45355

Files:
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  test/CodeGen/Thumb/umulo-32-legalisation-lowering.ll


Index: test/CodeGen/Thumb/umulo-32-legalisation-lowering.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb/umulo-32-legalisation-lowering.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=thumb-eabi   | FileCheck %s --check-prefixes CHECK,CHECK-LITTLE
+; RUN: llc < %s -mtriple=thumbeb-eabi | FileCheck %s --check-prefixes CHECK,CHECK-BIG
+
+define { i32, i8 } @umulo32(i32 %l, i32 %r) unnamed_addr #0 {
+; CHECK-LABEL: umulo32:
+; CHECK:                @ %bb.0: @ %start
+; CHECK-NEXT:           .save {r7, lr}
+; CHECK-NEXT:           push {r7, lr}
+; CHECK-LITTLE-NEXT:    movs r2, r1
+; CHECK-LITTLE-NEXT:    movs r1, #0
+; CHECK-NEXT:           movs r3, r1
+; CHECK-BIG-NEXT:       movs r1, r0
+; CHECK-BIG-NEXT:       movs r0, #0
+; CHECK-BIG-NEXT:       movs r2, r0
+; CHECK-NEXT:           bl __aeabi_lmul
+; CHECK-LITTLE-NEXT:    cmp  r1, #0
+; CHECK-BIG-NEXT:       movs r2, r0
+; CHECK-BIG-NEXT:       movs r0, r1
+; CHECK-BIG-NEXT:       cmp  r2, #0
+; CHECK-NEXT:           beq .LBB0_2
+; CHECK-NEXT:           @ %bb.1:
+; CHECK-LITTLE-NEXT:    movs r1, #1
+; CHECK-BIG-NEXT:       movs r2, #1
+; CHECK-NEXT:           .LBB0_2: @ %start
+; CHECK-BIG-NEXT:       movs r1, r2
+; CHECK-NEXT:           pop {r7}
+; CHECK-NEXT:           pop {r2}
+; CHECK-NEXT:           bx r2
+start:
+  %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %l, i32 %r) #2
+  %1 = extractvalue { i32, i1 } %0, 0
+  %2 = extractvalue { i32, i1 } %0, 1
+  %3 = zext i1 %2 to i8
+  %4 = insertvalue { i32, i8 } undef, i32 %1, 0
+  %5 = insertvalue { i32, i8 } %4, i8 %3, 1
+  ret { i32, i8 } %5
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) #1
+
+attributes #0 = { nounwind readnone uwtable }
+attributes #1 = { nounwind readnone speculatable }
+attributes #2 = { nounwind }
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3436,8 +3436,14 @@
       }
       assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
              "Ret value is a collection of constituent nodes holding result.");
-      BottomHalf = Ret.getOperand(0);
-      TopHalf = Ret.getOperand(1);
+      if(DAG.getDataLayout().isLittleEndian()) {
+        // Same as above.
+        BottomHalf = Ret.getOperand(0);
+        TopHalf = Ret.getOperand(1);
+      } else {
+        BottomHalf = Ret.getOperand(1);
+        TopHalf = Ret.getOperand(0);
+      }
     }
 
     if (isSigned) {


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