[llvm] r353589 - Recommit "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR""

[Jessica Paquette via llvm-commits]

Author: paquette
Date: Fri Feb  8 16:37:31 2019
New Revision: 353589

URL: http://llvm.org/viewvc/llvm-project?rev=353589&view=rev
Log:
Recommit "[GlobalISel] Introduce a generic floating point floor opcode, G_FFLOOR""

After r353586, we won't fail on the AMDGPU floor pattern that was killing the
importer before.

Modified:
    llvm/trunk/include/llvm/Support/TargetOpcodes.def
    llvm/trunk/include/llvm/Target/GenericOpcodes.td
    llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Modified: llvm/trunk/include/llvm/Support/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetOpcodes.def?rev=353589&r1=353588&r2=353589&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Support/TargetOpcodes.def Fri Feb  8 16:37:31 2019
@@ -530,6 +530,9 @@ HANDLE_TARGET_OPCODE(G_FSIN)
 /// Floating point square root.
 HANDLE_TARGET_OPCODE(G_FSQRT)
 
+/// Floating point floor.
+HANDLE_TARGET_OPCODE(G_FFLOOR)
+
 /// Generic AddressSpaceCast.
 HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
 

Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=353589&r1=353588&r2=353589&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Fri Feb  8 16:37:31 2019
@@ -579,6 +579,13 @@ def G_FSQRT : GenericInstruction {
   let hasSideEffects = 0;
 }
 
+// Floating point floor of a value.
+def G_FFLOOR : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1);
+  let hasSideEffects = 0;
+}
+
 //------------------------------------------------------------------------------
 // Opcodes for LLVM Intrinsics
 //------------------------------------------------------------------------------

Modified: llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=353589&r1=353588&r2=353589&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (original)
+++ llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td Fri Feb  8 16:37:31 2019
@@ -93,6 +93,7 @@ def : GINodeEquiv<G_FCOS, fcos>;
 def : GINodeEquiv<G_FSIN, fsin>;
 def : GINodeEquiv<G_FABS, fabs>;
 def : GINodeEquiv<G_FSQRT, fsqrt>;
+def : GINodeEquiv<G_FFLOOR, ffloor>;
 
 // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
 // complications that tablegen must take care of. For example, Predicates such

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=353589&r1=353588&r2=353589&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Fri Feb  8 16:37:31 2019
@@ -340,7 +340,10 @@
 # DEBUG: .. the first uncovered type index: 1, OK
 #
 # DEBUG-NEXT: G_FSQRT (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. the first uncovered type index: 1, OK
+# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_FFLOOR (opcode {{[0-9]+}}): 1 type index
+# DEBUG: .. type index coverage check SKIPPED: no rules defined
 
 # CHECK-NOT: ill-defined