[llvm] r353520 - [MIPS GlobalISel] Select any extending load and truncating store
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 8 06:27:23 PST 2019
Author: petar.avramovic
Date: Fri Feb 8 06:27:23 2019
New Revision: 353520
URL: http://llvm.org/viewvc/llvm-project?rev=353520&view=rev
Log:
[MIPS GlobalISel] Select any extending load and truncating store
Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and
G_SEXTLOAD. That is perform widenScalarDst to size given by the target
and avoid additional checks in common code. Targets can reorder or add
additional rules in LegalizeRuleSet for the opcode to achieve desired
behavior.
Select extending load that does not have specified type of extension
into zero extending load.
Select truncating store that stores number of bytes indicated by size
in MachineMemoperand.
Differential Revision: https://reviews.llvm.org/D57454
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=353520&r1=353519&r2=353520&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Fri Feb 8 06:27:23 2019
@@ -1208,13 +1208,6 @@ LegalizerHelper::widenScalar(MachineInst
return Legalized;
case TargetOpcode::G_LOAD:
- // For some types like i24, we might try to widen to i32. To properly handle
- // this we should be using a dedicated extending load, until then avoid
- // trying to legalize.
- if (alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) !=
- WideTy.getSizeInBits())
- return UnableToLegalize;
- LLVM_FALLTHROUGH;
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
Observer.changingInstr(MI);
Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=353520&r1=353519&r2=353520&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Fri Feb 8 06:27:23 2019
@@ -96,10 +96,15 @@ static unsigned selectLoadStoreOpCode(un
switch (MemSizeInBytes) {
case 4:
return Mips::SW;
+ case 2:
+ return Mips::SH;
+ case 1:
+ return Mips::SB;
default:
return Opc;
}
else
+ // Unspecified extending load is selected into zeroExtending load.
switch (MemSizeInBytes) {
case 4:
return Mips::LW;
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=353520&r1=353519&r2=353520&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Fri Feb 8 06:27:23 2019
@@ -36,7 +36,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
.lowerFor({{s32, s1}});
getActionDefinitionsBuilder({G_LOAD, G_STORE})
- .legalForCartesianProduct({p0, s32}, {p0});
+ .legalForTypesWithMemSize({{s32, p0, 8},
+ {s32, p0, 16},
+ {s32, p0, 32},
+ {p0, p0, 32}})
+ .minScalar(0, s32);
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
.legalForTypesWithMemSize({{s32, p0, 8},
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir?rev=353520&r1=353519&r2=353520&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir Fri Feb 8 06:27:23 2019
@@ -1,19 +1,24 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
-# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
-
-# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_sextload_flat_i32_i8)
-
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI
---
name: test_sextload_flat_i32_i8
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i32_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ ; SI-LABEL: name: test_sextload_flat_i32_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ ; VI-LABEL: name: test_sextload_flat_i32_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; VI: $vgpr0 = COPY [[ASHR]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0 = COPY %1
@@ -24,11 +29,19 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i32_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
- ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
- %0:_(p0) = COPY $vgpr0_vgpr1
+ ; SI-LABEL: name: test_sextload_flat_i32_i16
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
+ ; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ ; VI-LABEL: name: test_sextload_flat_i32_i16
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; VI: $vgpr0 = COPY [[ASHR]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0 = COPY %1
...
@@ -38,11 +51,20 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i31_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI-LABEL: name: test_sextload_flat_i31_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
+ ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI-LABEL: name: test_sextload_flat_i31_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
+ ; VI: $vgpr0 = COPY [[COPY2]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -54,11 +76,20 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i64_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; SI-LABEL: name: test_sextload_flat_i64_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; VI-LABEL: name: test_sextload_flat_i64_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0_vgpr1 = COPY %1
@@ -69,11 +100,20 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i64_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
- ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; SI-LABEL: name: test_sextload_flat_i64_i16
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
+ ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; VI-LABEL: name: test_sextload_flat_i64_i16
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ASHR]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0_vgpr1 = COPY %1
@@ -84,11 +124,16 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_sextload_flat_i64_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
- ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; SI-LABEL: name: test_sextload_flat_i64_i32
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ ; VI-LABEL: name: test_sextload_flat_i64_i32
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 0)
$vgpr0_vgpr1 = COPY %1
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir?rev=353520&r1=353519&r2=353520&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir Fri Feb 8 06:27:23 2019
@@ -1,19 +1,23 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
-# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
-
-# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_zextload_flat_i32_i8)
-
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI
---
name: test_zextload_flat_i32_i8
body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i32_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ ; SI-LABEL: name: test_zextload_flat_i32_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ ; VI-LABEL: name: test_zextload_flat_i32_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: $vgpr0 = COPY [[AND]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0 = COPY %1
@@ -24,11 +28,18 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i32_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
- ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
- %0:_(p0) = COPY $vgpr0_vgpr1
+ ; SI-LABEL: name: test_zextload_flat_i32_i16
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
+ ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ ; VI-LABEL: name: test_zextload_flat_i32_i16
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: $vgpr0 = COPY [[AND]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0 = COPY %1
...
@@ -38,11 +49,19 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i31_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI-LABEL: name: test_zextload_flat_i31_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
+ ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI-LABEL: name: test_zextload_flat_i31_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
+ ; VI: $vgpr0 = COPY [[COPY2]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -54,11 +73,19 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i64_i8
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; SI-LABEL: name: test_zextload_flat_i64_i8
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; VI-LABEL: name: test_zextload_flat_i64_i8
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
$vgpr0_vgpr1 = COPY %1
@@ -69,11 +96,19 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i64_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; SI-LABEL: name: test_zextload_flat_i64_i16
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; VI-LABEL: name: test_zextload_flat_i64_i16
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
$vgpr0_vgpr1 = COPY %1
@@ -84,11 +119,16 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1
- ; CHECK-LABEL: name: test_zextload_flat_i64_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; SI-LABEL: name: test_zextload_flat_i64_i32
+ ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ ; VI-LABEL: name: test_zextload_flat_i64_i32
+ ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 0)
$vgpr0_vgpr1 = COPY %1
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir?rev=353520&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir Fri Feb 8 06:27:23 2019
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+ define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+ define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name: load_store_i8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i8
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY1]], 0 :: (load 1 from %ir.py)
+ ; MIPS32: SB [[LBu]], [[COPY]], 0 :: (store 1 into %ir.px)
+ ; MIPS32: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %4:gprb(s32) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+ %3:gprb(s32) = COPY %4(s32)
+ G_STORE %3(s32), %0(p0) :: (store 1 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i16
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY1]], 0 :: (load 2 from %ir.py)
+ ; MIPS32: SH [[LHu]], [[COPY]], 0 :: (store 2 into %ir.px)
+ ; MIPS32: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %4:gprb(s32) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+ %3:gprb(s32) = COPY %4(s32)
+ G_STORE %3(s32), %0(p0) :: (store 2 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i32
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+ ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY1]], 0 :: (load 4 from %ir.py)
+ ; MIPS32: SW [[LW]], [[COPY]], 0 :: (store 4 into %ir.px)
+ ; MIPS32: RetRA
+ %0:gprb(p0) = COPY $a0
+ %1:gprb(p0) = COPY $a1
+ %2:gprb(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+ G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+ RetRA
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir?rev=353520&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir Fri Feb 8 06:27:23 2019
@@ -0,0 +1,145 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
+ define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
+ define void @load_store_i1(i1* %px, i1* %py) {entry: ret void}
+ define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+ define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+ define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name: load1_s8_to_load1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_load1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %2:_(s32) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load2_s16_to_load2_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load2_s16_to_load2_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.px)
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %2:_(s32) = G_LOAD %0(p0) :: (load 2 from %ir.px)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load_store_i1
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i1
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; MIPS32: G_STORE [[AND]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(s1) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+ G_STORE %2(s1), %0(p0) :: (store 1 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i8
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i8
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(s8) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+ G_STORE %2(s8), %0(p0) :: (store 1 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i16
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i16
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 2 from %ir.py)
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
+ ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 2 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(s16) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+ G_STORE %2(s16), %0(p0) :: (store 2 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i32
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.py)
+ ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store 4 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+ G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+ RetRA
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll?rev=353520&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Fri Feb 8 06:27:23 2019
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i8 @load1_s8_to_load1_s32(i8* %px) {
+; MIPS32-LABEL: load1_s8_to_load1_s32:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lbu $2, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i8, i8* %px
+ ret i8 %0
+}
+
+define i16 @load2_s16_to_load2_s32(i16* %px) {
+; MIPS32-LABEL: load2_s16_to_load2_s32:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lhu $2, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i16, i16* %px
+ ret i16 %0
+}
+
+define void @load_store_i1(i1* %px, i1* %py) {
+; MIPS32-LABEL: load_store_i1:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lbu $5, 0($5)
+; MIPS32-NEXT: lui $1, 0
+; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: and $1, $5, $1
+; MIPS32-NEXT: sb $1, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i1, i1* %py
+ store i1 %0, i1* %px
+ ret void
+}
+
+define void @load_store_i8(i8* %px, i8* %py) {
+; MIPS32-LABEL: load_store_i8:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lbu $5, 0($5)
+; MIPS32-NEXT: sb $5, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i8, i8* %py
+ store i8 %0, i8* %px
+ ret void
+}
+
+define void @load_store_i16(i16* %px, i16* %py) {
+; MIPS32-LABEL: load_store_i16:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lhu $5, 0($5)
+; MIPS32-NEXT: sh $5, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i16, i16* %py
+ store i16 %0, i16* %px
+ ret void
+}
+
+define void @load_store_i32(i32* %px, i32* %py) {
+; MIPS32-LABEL: load_store_i32:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lw $5, 0($5)
+; MIPS32-NEXT: sw $5, 0($4)
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i32, i32* %py
+ store i32 %0, i32* %px
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir?rev=353520&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir Fri Feb 8 06:27:23 2019
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
+ define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
+ define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
+
+...
+---
+name: load_store_i8
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i8
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py)
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
+ ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 1 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %4:_(s32) = G_LOAD %1(p0) :: (load 1 from %ir.py)
+ %3:_(s32) = COPY %4(s32)
+ G_STORE %3(s32), %0(p0) :: (store 1 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i16
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i16
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 2 from %ir.py)
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[LOAD]](s32)
+ ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 2 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %4:_(s32) = G_LOAD %1(p0) :: (load 2 from %ir.py)
+ %3:_(s32) = COPY %4(s32)
+ G_STORE %3(s32), %0(p0) :: (store 2 into %ir.px)
+ RetRA
+
+...
+---
+name: load_store_i32
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; MIPS32-LABEL: name: load_store_i32
+ ; MIPS32: liveins: $a0, $a1
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.py)
+ ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store 4 into %ir.px)
+ ; MIPS32: RetRA
+ %0:_(p0) = COPY $a0
+ %1:_(p0) = COPY $a1
+ %2:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.py)
+ G_STORE %2(s32), %0(p0) :: (store 4 into %ir.px)
+ RetRA
+
+...
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