[PATCH] D57857: [PowerPC] custom lower `v2f64 fpext v2f32`

[Ahsan Saghir via Phabricator via llvm-commits]

saghir requested changes to this revision.
saghir added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9526
+  if (Op.getValueType() != MVT::v2f64 ||
+    Op.getOperand(0).getValueType() != MVT::v2f32)
+    return SDValue();
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Formatting


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9544
+        return SDValue();
+      // Generate new load dag.
+      LoadSDNode *LD = cast<LoadSDNode>(LdOp);
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Minor: `DAG` instead of `dag`.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:407
 
+      /// Custom expend v4f32 to v2f64.
+      FP_EXTEND_LHW,
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`expand` maybe?


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:1089
 }
+
 let Predicates = [IsBigEndian, HasVSX, HasOnlySwappingMemOps] in {
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You may get rid of this new line.


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Comment at: llvm/test/CodeGen/PowerPC/reduce_scalarization.ll:7
+; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
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Do we need `RUN` on all these lines?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57857/new/

https://reviews.llvm.org/D57857