[PATCH] D57833: [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'd like to see testcases for all the possible add/sub opcodes, if it isn't too much work.



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Comment at: lib/Target/ARM/ARMBaseInstrInfo.cpp:2659
+      (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8) &&
+      OI->getOperand(0).getReg() == SrcReg &&
+      OI->getOperand(2).getReg() == SrcReg2)
----------------
The corresponding ARM/Thumb2 code checks for ADDrr; should we add the corresponding check for tADDrr? 
 Or does that not work for some reason?


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Comment at: lib/Target/ARM/ARMBaseInstrInfo.cpp:2679
   case ARM::tSUBi8:
   case ARM::tMUL:
     IsThumb1 = true;
----------------
I guess it's sort of orthogonal to this patch, but this list isn't complete, if it's supposed to be a list of instructions which update the NZ bits.  (Missing tADC, tSBC, tAND, tORR, tEOR, tBIC, tMVN, tASRri, tASRrr, tROR, I think.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57833/new/

https://reviews.llvm.org/D57833