[PATCH] D57401: [DAGCombiner] fold add/sub with bool operand based on target's boolean contents
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 7 09:43:38 PST 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL353433: [DAGCombiner] fold add/sub with bool operand based on target's boolean contents (authored by spatel, committed by ).
Herald added a project: LLVM.
Changed prior to commit:
https://reviews.llvm.org/D57401?vs=184380&id=185797#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D57401/new/
https://reviews.llvm.org/D57401
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/PowerPC/bool-math.ll
llvm/trunk/test/CodeGen/PowerPC/signbit-shift.ll
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2300,10 +2300,12 @@
if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
return V;
- // add (sext i1), X -> sub X, (zext i1)
+ // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
+ // rather than 'add 0/-1' (the zext should get folded).
+ // add (sext i1 Y), X --> sub X, (zext i1 Y)
if (N0.getOpcode() == ISD::SIGN_EXTEND &&
- N0.getOperand(0).getValueType() == MVT::i1 &&
- !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
+ N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
+ TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
}
@@ -2751,6 +2753,17 @@
if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
return V;
+ // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
+ // rather than 'sub 0/1' (the sext should get folded).
+ // sub X, (zext i1 Y) --> add X, (sext i1 Y)
+ if (N1.getOpcode() == ISD::ZERO_EXTEND &&
+ N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
+ TLI.getBooleanContents(VT) ==
+ TargetLowering::ZeroOrNegativeOneBooleanContent) {
+ SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
+ return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
+ }
+
// fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
Index: llvm/trunk/test/CodeGen/PowerPC/bool-math.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/bool-math.ll
+++ llvm/trunk/test/CodeGen/PowerPC/bool-math.ll
@@ -83,9 +83,8 @@
define i32 @low_bit_select_constants_bigger_false_same_size_result(i32 %x) {
; CHECK-LABEL: low_bit_select_constants_bigger_false_same_size_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: not 3, 3
; CHECK-NEXT: clrldi 3, 3, 63
-; CHECK-NEXT: subfic 3, 3, 43
+; CHECK-NEXT: ori 3, 3, 42
; CHECK-NEXT: blr
%a = and i32 %x, 1
%c = icmp eq i32 %a, 0
@@ -96,9 +95,8 @@
define i64 @low_bit_select_constants_bigger_false_wider_result(i32 %x) {
; CHECK-LABEL: low_bit_select_constants_bigger_false_wider_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: not 3, 3
; CHECK-NEXT: clrldi 3, 3, 63
-; CHECK-NEXT: subfic 3, 3, 27
+; CHECK-NEXT: ori 3, 3, 26
; CHECK-NEXT: blr
%a = and i32 %x, 1
%c = icmp eq i32 %a, 0
@@ -109,9 +107,8 @@
define i16 @low_bit_select_constants_bigger_false_narrower_result(i32 %x) {
; CHECK-LABEL: low_bit_select_constants_bigger_false_narrower_result:
; CHECK: # %bb.0:
-; CHECK-NEXT: nor 3, 3, 3
-; CHECK-NEXT: clrlwi 3, 3, 31
-; CHECK-NEXT: subfic 3, 3, 37
+; CHECK-NEXT: clrldi 3, 3, 63
+; CHECK-NEXT: ori 3, 3, 36
; CHECK-NEXT: blr
%a = and i32 %x, 1
%c = icmp eq i32 %a, 0
Index: llvm/trunk/test/CodeGen/PowerPC/signbit-shift.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/signbit-shift.ll
+++ llvm/trunk/test/CodeGen/PowerPC/signbit-shift.ll
@@ -69,9 +69,8 @@
define i32 @add_sext_ifpos(i32 %x) {
; CHECK-LABEL: add_sext_ifpos:
; CHECK: # %bb.0:
-; CHECK-NEXT: nor 3, 3, 3
-; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: addi 3, 3, 42
+; CHECK-NEXT: srwi 3, 3, 31
+; CHECK-NEXT: addi 3, 3, 41
; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1
%e = sext i1 %c to i32
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