[PATCH] D57735: [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions.

Thu Feb 7 04:37:13 PST 2019

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM but a PR40206 test case as well would be useful

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Comment at: test/CodeGen/X86/pr34080.ll:73
 ; SSE2-SCHEDULE-NEXT:    fldcw -2(%rbp)
-; SSE2-SCHEDULE-NEXT:    fmul %st, %st(1)
 ; SSE2-SCHEDULE-NEXT:    movw %ax, -2(%rbp)
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dim wrote:
> craig.topper wrote:
> > This looks like we were still miscompiling this test despite this bug being closed
> Hm yes, in rL321424 @RKSimon added a pr34080-2.ll test case, but didn't touch this one, for some reason.
I think it shows the limits of the fix I put in - this approach seems a lot more thorough

Repository:
  rL LLVM

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  https://reviews.llvm.org/D57735/new/

https://reviews.llvm.org/D57735