[PATCH] D57862: [AArch64] Fix condition for "high-vector" DUP optimizations.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added a reviewer: fhahn.
Herald added subscribers: kristof.beyls, javed.absar.
Herald added a project: LLVM.

AArch64 NEON has a bunch of instructions with a "2" suffix that extract the top half of the source vectors, instead of the bottom half.  We have some DAGCombines to try to take advantage of that.  However, they assumed that any EXTRACT_VECTOR was extracting the high half of the vector in question.

This issue has apparently existed since the AArch64 backend was merged.

Fixes https://bugs.llvm.org/show_bug.cgi?id=40632 .


Repository:
  rL LLVM

https://reviews.llvm.org/D57862

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-vabs.ll
  test/CodeGen/AArch64/arm64-vadd.ll
  test/CodeGen/AArch64/arm64-vmul.ll

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