[llvm] r353330 - [SystemZ] Improved handling of the @llvm.ctlz intrinsic.

Wed Feb 6 11:23:31 PST 2019

Author: jonpa
Date: Wed Feb  6 11:23:31 2019
New Revision: 353330

URL: http://llvm.org/viewvc/llvm-project?rev=353330&view=rev
Log:
[SystemZ]  Improved handling of the @llvm.ctlz intrinsic.

Since SystemZ supports counting of leading zeros with the FLOGR instruction,
isCheapToSpeculateCtlz() should return true, which it now does.

ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which
is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only
expanded to CTLZ if it is Legal or Custom.

Review: Ulrich Weigand
https://reviews.llvm.org/D57710

Added:
    llvm/trunk/test/CodeGen/SystemZ/scalar-ctlz.ll
Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=353330&r1=353329&r2=353330&view=diff
==============================================================================

--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Feb  6 11:23:31 2019
@@ -249,6 +249,7 @@ SystemZTargetLowering::SystemZTargetLowe
 
   // We have native support for a 64-bit CTLZ, via FLOGR.
   setOperationAction(ISD::CTLZ, MVT::i32, Promote);
+  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
 
   // Give LowerOperation the chance to replace 64-bit ORs with subregs.

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=353330&r1=353329&r2=353330&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Wed Feb  6 11:23:31 2019
@@ -391,6 +391,7 @@ public:
       return TypeWidenVector;
     return TargetLoweringBase::getPreferredVectorAction(VT);
   }
+  bool isCheapToSpeculateCtlz() const override { return true; }
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
                          EVT) const override;
   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;

Added: llvm/trunk/test/CodeGen/SystemZ/scalar-ctlz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/scalar-ctlz.ll?rev=353330&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/scalar-ctlz.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/scalar-ctlz.ll Wed Feb  6 11:23:31 2019
@@ -0,0 +1,107 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+;
+; FIXME: two consecutive immediate adds not fused in i16/i8 functions.
+
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i16 @llvm.ctlz.i16(i16, i1)
+declare i8 @llvm.ctlz.i8(i8, i1)
+
+define i64 @f0(i64 %arg) {
+; CHECK-LABEL: f0:
+; CHECK-LABEL: %bb.0:
+; CHECK-NOT:   %bb.1:
+; CHECK: flogr
+  %1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 false)
+  ret i64 %1
+}
+
+define i64 @f1(i64 %arg) {
+; CHECK-LABEL: f1:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: flogr
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i64 @llvm.ctlz.i64(i64 %arg, i1 true)
+  ret i64 %1
+}
+
+define i32 @f2(i32 %arg) {
+; CHECK-LABEL: f2:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: llgfr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i32 @llvm.ctlz.i32(i32 %arg, i1 false)
+  ret i32 %1
+}
+
+define i32 @f3(i32 %arg) {
+; CHECK-LABEL: f3:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: llgfr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i32 @llvm.ctlz.i32(i32 %arg, i1 true)
+  ret i32 %1
+}
+
+define i16 @f4(i16 %arg) {
+; CHECK-LABEL: f4:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: # kill
+; CHECK-NEXT: llghr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: ahi   %r2, -16
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)
+  ret i16 %1
+}
+
+define i16 @f5(i16 %arg) {
+; CHECK-LABEL: f5:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: # kill
+; CHECK-NEXT: llghr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: ahi   %r2, -16
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 true)
+  ret i16 %1
+}
+
+define i8 @f6(i8 %arg) {
+; CHECK-LABEL: f6:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: # kill
+; CHECK-NEXT: llgcr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: ahi   %r2, -24
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i8 @llvm.ctlz.i8(i8 %arg, i1 false)
+  ret i8 %1
+}
+
+define i8 @f7(i8 %arg) {
+; CHECK-LABEL: f7:
+; CHECK-LABEL: %bb.0:
+; CHECK-NEXT: # kill
+; CHECK-NEXT: llgcr %r0, %r2
+; CHECK-NEXT: flogr %r2, %r0
+; CHECK-NEXT: aghi  %r2, -32
+; CHECK-NEXT: ahi   %r2, -24
+; CHECK-NEXT: # kill
+; CHECK-NEXT: br %r14
+  %1 = tail call i8 @llvm.ctlz.i8(i8 %arg, i1 true)
+  ret i8 %1
+}


