[PATCH] D57141: [RISCV][WIP] Add implied zero offset load/store alias pattern

[James Clarke via Phabricator via llvm-commits]

jrtc27 updated this revision to Diff 185418.
jrtc27 added a comment.

Support all memory instructions; add test coverage


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57141/new/

https://reviews.llvm.org/D57141

Files:
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoC.td
  lib/Target/RISCV/RISCVInstrInfoD.td
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/MC/RISCV/rv32fc-aliases-valid.s
  test/MC/RISCV/rv32i-aliases-valid.s
  test/MC/RISCV/rv64c-aliases-valid.s
  test/MC/RISCV/rv64i-aliases-valid.s
  test/MC/RISCV/rvc-aliases-valid.s
  test/MC/RISCV/rvd-aliases-valid.s
  test/MC/RISCV/rvdc-aliases-valid.s
  test/MC/RISCV/rvf-aliases-valid.s

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