[llvm] r353202 - AMDGPU: Fix assert on trunc from bitcast of build_vector

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue Feb  5 11:23:57 2019
New Revision: 353202

URL: http://llvm.org/viewvc/llvm-project?rev=353202&view=rev
Log:
AMDGPU: Fix assert on trunc from bitcast of build_vector

The v2i64 argument is lowered to a bitcast of v4i32 build_vector.
This would then attempt to use the i32-element as the source of the
vector truncate. This really would need to collect 2 elements from the
build_vector to produce the intended truncate.

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/trunk/test/CodeGen/AMDGPU/trunc-combine.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=353202&r1=353201&r2=353202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Tue Feb  5 11:23:57 2019
@@ -3088,7 +3088,7 @@ SDValue AMDGPUTargetLowering::performTru
   SDValue Src = N->getOperand(0);
 
   // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
-  if (Src.getOpcode() == ISD::BITCAST) {
+  if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
     SDValue Vec = Src.getOperand(0);
     if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
       SDValue Elt0 = Vec.getOperand(0);

Modified: llvm/trunk/test/CodeGen/AMDGPU/trunc-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/trunc-combine.ll?rev=353202&r1=353201&r2=353202&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/trunc-combine.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/trunc-combine.ll Tue Feb  5 11:23:57 2019
@@ -1,3 +1,4 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
 
 ; Make sure high constant 0 isn't pointlessly materialized
@@ -25,7 +26,7 @@ define i32 @trunc_bitcast_i64_lshr_32_i3
 ; GCN: _load_dword
 ; GCN-NOT: _load_dword
 ; GCN-NOT: v_mov_b32
-; GCN: v_add_u16_e32 v0, 4, v0
+; VI: v_add_u16_e32 v0, 4, v0
 define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
   %load0 = load i32, i32 addrspace(1)* undef
   %load1 = load i32, i32 addrspace(1)* null
@@ -42,7 +43,7 @@ define i16 @trunc_bitcast_v2i32_to_i16(<
 ; GCN: _load_dword
 ; GCN-NOT: _load_dword
 ; GCN-NOT: v_mov_b32
-; GCN: v_add_u16_e32 v0, 4, v0
+; VI: v_add_u16_e32 v0, 4, v0
 define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
   %load0 = load float, float addrspace(1)* undef
   %load1 = load float, float addrspace(1)* null
@@ -80,3 +81,18 @@ bb:
   store <2 x i16> %tmp14, <2 x i16> addrspace(1)* %tmp15, align 4
   ret void
 }
+
+; GCN-LABEL: {{^}}trunc_v2i64_arg_to_v2i16:
+; GCN: v_lshlrev_b32_e32 v1, 16, v2
+
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+
+; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+
+; GCN-NEXT: s_setpc_b64
+define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {
+  %trunc = trunc <2 x i64> %arg0 to <2 x i16>
+  ret <2 x i16> %trunc
+}