[PATCH] D57748: AMDGPU: Add inverse ballot intrinsic
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 5 06:34:29 PST 2019
arsenm added inline comments.
================
Comment at: test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.ll:26
+}
+
+declare i1 @llvm.amdgcn.inverse.ballot(i64)
----------------
cwabbott wrote:
> arsenm wrote:
> > Need to add a few more tests with more complex situations (particularly one with a uniform phi, and one with a divergent phi)
> Why would having a phi node change anything? As far as I can see these tests cover the only two cases that really matter for lowering this (input in SGPR and input in VGPR).
I'm specifically worried about the change isVGPRToSGPRCopy. Phi and i1 handling has been a problematic area in SIFixSGPRCopies.
I would probably be more comfortable using a pseudo instruction for this until this point rather than making a regular COPY to VReg_1 legal
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rL LLVM
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https://reviews.llvm.org/D57748/new/
https://reviews.llvm.org/D57748
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