[llvm] r353138 - [X86] Add test case from PR40529. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Feb  4 20:48:23 2019
New Revision: 353138

URL: http://llvm.org/viewvc/llvm-project?rev=353138&view=rev
Log:
[X86] Add test case from PR40529. NFC

Added:
    llvm/trunk/test/CodeGen/X86/pr40529.ll

Added: llvm/trunk/test/CodeGen/X86/pr40529.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr40529.ll?rev=353138&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr40529.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr40529.ll Mon Feb  4 20:48:23 2019
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s
+
+define x86_fp80 @rem_pio2l_min(x86_fp80 %z) {
+; CHECK-LABEL: rem_pio2l_min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT:    movw $3199, -{{[0-9]+}}(%rsp) # imm = 0xC7F
+; CHECK-NEXT:    fldcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fistl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fldcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fisubl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    flds {{.*}}(%rip)
+; CHECK-NEXT:    fmul %st, %st(1)
+; CHECK-NEXT:    fnstcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movzwl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT:    movw $3199, -{{[0-9]+}}(%rsp) # imm = 0xC7F
+; CHECK-NEXT:    fldcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fistl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fldcw -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fisubl -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fmulp %st, %st(1)
+; CHECK-NEXT:    retq
+entry:
+  %conv = fptosi x86_fp80 %z to i32
+  %conv1 = sitofp i32 %conv to x86_fp80
+  %sub = fsub x86_fp80 %z, %conv1
+  %mul = fmul x86_fp80 %sub, 0xK40178000000000000000
+  %conv2 = fptosi x86_fp80 %mul to i32
+  %conv3 = sitofp i32 %conv2 to x86_fp80
+  %sub4 = fsub x86_fp80 %mul, %conv3
+  %mul5 = fmul x86_fp80 %sub4, 0xK40178000000000000000
+  ret x86_fp80 %mul5
+}