[PATCH] D57598: [VPLAN] Determine Vector Width programmatically.

[Nikolay Panchenko via Phabricator via llvm-commits]

npanchen added inline comments.


================
Comment at: lib/Transforms/Vectorize/LoopVectorize.cpp:7103
+    for (auto I = B->begin(), E=B->end(); I!=E; ++I ) {
+      if (!isa<LoadInst>(*I) && !isa<StoreInst>(*I))
+        continue;
----------------
fpetrogalli wrote:
> npanchen wrote:
> > For a cases when load and store instructions were hoisted out of the loop, this function will return WidestVectorRegBits, which could be >= 128.
> Sorry I don't understand this comment, could you please explain it with and example? Also, given that my understanding is that you want me to use `getSmallestAndWidestTypes`, is the comment still valid? Because I think that by using `getSmallestAndWidestTypes` I essentially will remove my custom code.
The example I was thinking about is pretty simple:


```
#pragma clang loop vectorize(enable)
for (i = 0; i < n; ++i) {
  red += i;
}

```
After some optimization the loop body can look like:


```
loop_body:
%1 = phi i64     %i_init,              %i
%2 = phi i32     %red_init,          %red
%red = %2 + %1
%i = %1 + 1
cmp %i, %n
```

In this case guessVPlanVF() will not find any LD/ST instruction, thus Max will be equal to 1 and WidestVectorRegBits will be returned. 
For example, in case of SKX WidestVectorRegBits = 512.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57598/new/

https://reviews.llvm.org/D57598