[llvm] r353058 - [GlobalISel] Add IRTranslator support for G_FFLOOR

[Jessica Paquette via llvm-commits]

Author: paquette
Date: Mon Feb  4 09:15:34 2019
New Revision: 353058

URL: http://llvm.org/viewvc/llvm-project?rev=353058&view=rev
Log:
[GlobalISel] Add IRTranslator support for G_FFLOOR

Follow-up to https://reviews.llvm.org/D57484

Adds G_FFLOOR to translateKnownIntrinsic and update arm64-irtranslator.ll.

Differential Revision: https://reviews.llvm.org/D57485

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=353058&r1=353057&r2=353058&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Mon Feb  4 09:15:34 2019
@@ -1077,6 +1077,11 @@ bool IRTranslator::translateKnownIntrins
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
     return true;
+  case Intrinsic::floor:
+    MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
   case Intrinsic::cos:
     MIRBuilder.buildInstr(TargetOpcode::G_FCOS)
         .addDef(getOrCreateVReg(CI))

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=353058&r1=353057&r2=353058&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Mon Feb  4 09:15:34 2019
@@ -2324,6 +2324,14 @@ define float @test_sqrt_f32(float %x) {
   ret float %y
 }
 
+declare float @llvm.floor.f32(float)
+define float @test_floor_f32(float %x) {
+  ; CHECK-LABEL: name:            test_floor_f32
+  ; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}
+  %y = call float @llvm.floor.f32(float %x)
+  ret float %y
+}
+
 ; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i32
 ; CHECK: %1:_(s384) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load 48 from %ir.ptr, align 64)
 define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %ptr) {