[llvm] r352978 - GlobalISel: Implement widenScalar for G_EXTRACT vector sources
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 2 15:56:01 PST 2019
Author: arsenm
Date: Sat Feb 2 15:56:00 2019
New Revision: 352978
URL: http://llvm.org/viewvc/llvm-project?rev=352978&view=rev
Log:
GlobalISel: Implement widenScalar for G_EXTRACT vector sources
Handle the basic element extract case.
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=352978&r1=352977&r2=352978&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Sat Feb 2 15:56:00 2019
@@ -942,6 +942,32 @@ LegalizerHelper::widenScalar(MachineInst
switch (MI.getOpcode()) {
default:
return UnableToLegalize;
+ case TargetOpcode::G_EXTRACT: {
+ if (TypeIdx != 1)
+ return UnableToLegalize;
+
+ unsigned SrcReg = MI.getOperand(1).getReg();
+ LLT SrcTy = MRI.getType(SrcReg);
+ if (!SrcTy.isVector())
+ return UnableToLegalize;
+
+ unsigned DstReg = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ if (DstTy != SrcTy.getElementType())
+ return UnableToLegalize;
+
+ unsigned Offset = MI.getOperand(2).getImm();
+ if (Offset % SrcTy.getScalarSizeInBits() != 0)
+ return UnableToLegalize;
+
+ widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
+
+ MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
+ Offset);
+ widenScalarDst(MI, WideTy.getScalarType(), 0);
+
+ return Legalized;
+ }
case TargetOpcode::G_MERGE_VALUES: {
if (TypeIdx != 1)
return UnableToLegalize;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=352978&r1=352977&r2=352978&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Sat Feb 2 15:56:00 2019
@@ -439,6 +439,24 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
const LLT &Ty1 = Query.Types[1];
return (Ty0.getSizeInBits() % 16 == 0) &&
(Ty1.getSizeInBits() % 16 == 0);
+ })
+ .widenScalarIf(
+ [=](const LegalityQuery &Query) {
+ const LLT &Ty0 = Query.Types[0];
+ const LLT &Ty1 = Query.Types[1];
+ return (Ty1.getScalarSizeInBits() < 16);
+ },
+ // TODO Use generic LegalizeMutation
+ [](const LegalityQuery &Query) {
+ LLT Ty1 = Query.Types[1];
+ unsigned NewEltSizeInBits =
+ std::max(1 << Log2_32_Ceil(Ty1.getScalarSizeInBits()), 16);
+ if (Ty1.isVector()) {
+ return std::make_pair(1, LLT::vector(Ty1.getNumElements(),
+ NewEltSizeInBits));
+ }
+
+ return std::make_pair(1, LLT::scalar(NewEltSizeInBits));
});
// TODO: vectors of pointers
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir?rev=352978&r1=352977&r2=352978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir Sat Feb 2 15:56:00 2019
@@ -103,3 +103,135 @@ body: |
%1:_(s32) = G_EXTRACT %0, 64
S_ENDPGM implicit %1
...
+
+---
+name: extract_s8_v4s8_offset0
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v4s8_offset0
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 0
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<4 x s8>) = G_IMPLICIT_DEF
+ %1:_(s8) = G_EXTRACT %0, 0
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_s8_v4s8_offset8
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v4s8_offset8
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 16
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<4 x s8>) = G_IMPLICIT_DEF
+ %1:_(s8) = G_EXTRACT %0, 8
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_s8_v4s8_offset16
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v4s8_offset16
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 32
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<4 x s8>) = G_IMPLICIT_DEF
+ %1:_(s8) = G_EXTRACT %0, 16
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_s8_v4s8_offset24
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v4s8_offset24
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<4 x s16>), 48
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<4 x s8>) = G_IMPLICIT_DEF
+ %1:_(s8) = G_EXTRACT %0, 24
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_s8_v3s8_offset16
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v3s8_offset16
+ ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<3 x s16>), 32
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<3 x s8>) = G_IMPLICIT_DEF
+ %1:_(s8) = G_EXTRACT %0, 16
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_s8_v5s1_offset4
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_s8_v5s1_offset4
+ ; CHECK: [[DEF:%[0-9]+]]:_(<5 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[DEF]](<5 x s16>), 80
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(<5 x s1>) = G_IMPLICIT_DEF
+ %1:_(s1) = G_EXTRACT %0, 5
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: extract_v2s16_v4s16_offset32
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_v2s16_v4s16_offset32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 32
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+ %0:_(<4 x s16>) = G_IMPLICIT_DEF
+ %1:_(<2 x s16>) = G_EXTRACT %0, 32
+ $vgpr0 = COPY %1
+...
+
+---
+name: extract_v2s16_v6s16_offset32
+legalized: true
+
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: extract_v2s16_v6s16_offset32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[DEF]](<6 x s16>), 32
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
+ %0:_(<6 x s16>) = G_IMPLICIT_DEF
+ %1:_(<2 x s16>) = G_EXTRACT %0, 32
+ $vgpr0 = COPY %1
+...
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