[PATCH] D57504: RFC: EVL Prototype & Roadmap for vector predication in LLVM

[Jacob Lifshay via Phabricator via llvm-commits]

programmerjake added inline comments.


================
Comment at: include/llvm/IR/Intrinsics.td:1132
+                                LLVMMatchType<0>,
+                                LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                llvm_i32_ty]>;
----------------
simoll wrote:
> programmerjake wrote:
> > We will need to change the mask parameter length to allow for mask lengths that are a divisor of the main vector length.
> > See http://lists.llvm.org/pipermail/llvm-dev/2019-February/129845.html
> Can we make the vector length operate at the granularity of the mask?
> 
> In your case [1] that would mean that the AVL refers to multiples of the short element vector (eg `<3 x float>`).
> 
> [1] http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html
I was initially assuming that the vector length would be in the granularity of the mask.
That would work for my ISA extension. I think that would work for the RISC-V V extension, would have to double check, or get someone who's working on it to check. I don't think that would work without needing to multiply the vector length on AVX512, assuming a shift is used to generate the mask. I have no clue for ARM SVE or other architectures.


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