[PATCH] D57504: RFC: EVL Prototype & Roadmap for vector predication in LLVM

Fri Feb 1 02:02:14 PST 2019

simoll marked an inline comment as done.
simoll added inline comments.

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Comment at: docs/Proposals/VectorPredication.rst:19
+
+The Explicit Vector Length (EVL) extension [EvlRFC]_ can be a first step towards native vector predication.
+The EVL prototype in this patch demonstrates the following concepts:
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greened wrote:
> This document seems to overload "EVL" to mean both predication and an explicit vector length.  Of course predication can be used to simulate the effects of a vector length value on targets that don't have a way to specify an explicit vector length.
> 
> Can we keep the two concepts distinct in this document?  It's confusing to see "EVL" when discussing predication.  In particular, everything in `SelectionDAG` uses the "EVL" name to represent both concepts.  Can we come up with something more accurate?
"EVL" is really just the working title of the whole extension. It is my understanding that the explicit vector length parameter is just part of the predicate and not dinstinct from it (eg the conceptual predicate is a composite of the bit mask and the vector length).

How about naming the extension "VP" for "vector predication" (vp_fadd, llvm.vp.*)..?

Repository:
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