[PATCH] D57559: GlobalISel: Implement narrowScalar for shift main type

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, dsanders, paquette, aditya_nandakumar, volkan.
Herald added subscribers: Petar.Avramovic, javed.absar, kristof.beyls, rovka, nhaehnle, wdng, jvesely.

This is pretty much directly ported from SelectionDAG. Doesn't include
the shift by non-constant but known bits version, since there isn't a
globalisel version of computeKnownBits yet.

      

This shows a disadvantage of targets not specifically which type
should be used for the shift amount. If type 0 is legalized before
type 1, the operations on the shift amount type use the wider type
(which are also less likely to legalize). This can be avoided by
targets specifying legalization actions on type 1 earlier than for
type 0.


https://reviews.llvm.org/D57559

Files:
  include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  lib/Target/AArch64/AArch64LegalizerInfo.cpp
  lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
  test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
  test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

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