[llvm] r352807 - [RISCV] Add RV64F codegen support
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 31 14:48:39 PST 2019
Author: asb
Date: Thu Jan 31 14:48:38 2019
New Revision: 352807
URL: http://llvm.org/viewvc/llvm-project?rev=352807&view=rev
Log:
[RISCV] Add RV64F codegen support
This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.
Differential Revision: https://reviews.llvm.org/D53235
Added:
llvm/trunk/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
llvm/trunk/test/CodeGen/RISCV/rv64f-float-convert.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/trunk/test/CodeGen/RISCV/float-arith.ll
llvm/trunk/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-convert.ll
llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-imm.ll
llvm/trunk/test/CodeGen/RISCV/float-mem.ll
llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Thu Jan 31 14:48:38 2019
@@ -137,6 +137,9 @@ RISCVTargetLowering::RISCVTargetLowering
setOperationAction(Op, MVT::f32, Expand);
}
+ if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
+ setOperationAction(ISD::BITCAST, MVT::i32, Custom);
+
if (Subtarget.hasStdExtD()) {
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
@@ -338,6 +341,17 @@ SDValue RISCVTargetLowering::LowerOperat
return lowerFRAMEADDR(Op, DAG);
case ISD::RETURNADDR:
return lowerRETURNADDR(Op, DAG);
+ case ISD::BITCAST: {
+ assert(Subtarget.is64Bit() && Subtarget.hasStdExtF() &&
+ "Unexpected custom legalisation");
+ SDLoc DL(Op);
+ SDValue Op0 = Op.getOperand(0);
+ if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
+ return SDValue();
+ SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
+ SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
+ return FPConv;
+ }
}
}
@@ -579,6 +593,18 @@ void RISCVTargetLowering::ReplaceNodeRes
return;
Results.push_back(customLegalizeToWOp(N, DAG));
break;
+ case ISD::BITCAST: {
+ assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+ Subtarget.hasStdExtF() && "Unexpected custom legalisation");
+ SDLoc DL(N);
+ SDValue Op0 = N->getOperand(0);
+ if (Op0.getValueType() != MVT::f32)
+ return;
+ SDValue FPConv =
+ DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
+ break;
+ }
}
}
@@ -633,6 +659,38 @@ SDValue RISCVTargetLowering::PerformDAGC
return SDValue();
break;
}
+ case RISCVISD::FMV_X_ANYEXTW_RV64: {
+ SDLoc DL(N);
+ SDValue Op0 = N->getOperand(0);
+ // If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the
+ // conversion is unnecessary and can be replaced with an ANY_EXTEND
+ // of the FMV_W_X_RV64 operand.
+ if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
+ SDValue AExtOp =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0));
+ return DCI.CombineTo(N, AExtOp);
+ }
+
+ // This is a target-specific version of a DAGCombine performed in
+ // DAGCombiner::visitBITCAST. It performs the equivalent of:
+ // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
+ // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
+ if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
+ !Op0.getNode()->hasOneUse())
+ break;
+ SDValue NewFMV = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64,
+ Op0.getOperand(0));
+ APInt SignBit = APInt::getSignMask(32).sext(64);
+ if (Op0.getOpcode() == ISD::FNEG) {
+ return DCI.CombineTo(N,
+ DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV,
+ DAG.getConstant(SignBit, DL, MVT::i64)));
+ }
+ assert(Op0.getOpcode() == ISD::FABS);
+ return DCI.CombineTo(N,
+ DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
+ DAG.getConstant(~SignBit, DL, MVT::i64)));
+ }
}
return SDValue();
@@ -874,7 +932,7 @@ static bool CC_RISCV(const DataLayout &D
assert(XLen == 32 || XLen == 64);
MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
if (ValVT == MVT::f32) {
- LocVT = MVT::i32;
+ LocVT = XLenVT;
LocInfo = CCValAssign::BCvt;
}
@@ -1047,6 +1105,10 @@ static SDValue convertLocVTToValVT(Selec
case CCValAssign::Full:
break;
case CCValAssign::BCvt:
+ if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
+ Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
+ break;
+ }
Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
break;
}
@@ -1082,6 +1144,10 @@ static SDValue convertValVTToLocVT(Selec
case CCValAssign::Full:
break;
case CCValAssign::BCvt:
+ if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
+ Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val);
+ break;
+ }
Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
break;
}
@@ -1108,9 +1174,12 @@ static SDValue unpackFromMemLoc(Selectio
llvm_unreachable("Unexpected CCValAssign::LocInfo");
case CCValAssign::Full:
case CCValAssign::Indirect:
+ case CCValAssign::BCvt:
ExtType = ISD::NON_EXTLOAD;
break;
}
+ if (ValVT == MVT::f32)
+ LocVT = MVT::f32;
Val = DAG.getExtLoad(
ExtType, DL, LocVT, Chain, FIN,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT);
@@ -1759,6 +1828,10 @@ const char *RISCVTargetLowering::getTarg
return "RISCVISD::DIVUW";
case RISCVISD::REMUW:
return "RISCVISD::REMUW";
+ case RISCVISD::FMV_W_X_RV64:
+ return "RISCVISD::FMV_W_X_RV64";
+ case RISCVISD::FMV_X_ANYEXTW_RV64:
+ return "RISCVISD::FMV_X_ANYEXTW_RV64";
}
return nullptr;
}
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Thu Jan 31 14:48:38 2019
@@ -41,7 +41,14 @@ enum NodeType : unsigned {
// at instruction selection time.
DIVW,
DIVUW,
- REMUW
+ REMUW,
+ // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast
+ // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X.
+ // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
+ // This is a more convenient semantic for producing dagcombines that remove
+ // unnecessary GPR->FPR->GPR moves.
+ FMV_W_X_RV64,
+ FMV_X_ANYEXTW_RV64
};
}
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Thu Jan 31 14:48:38 2019
@@ -12,6 +12,20 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
+// RISC-V specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+def SDT_RISCVFMV_W_X_RV64
+ : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
+def SDT_RISCVFMV_X_ANYEXTW_RV64
+ : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
+
+def riscv_fmv_w_x_rv64
+ : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>;
+def riscv_fmv_x_anyextw_rv64
+ : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>;
+
+//===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
@@ -333,3 +347,37 @@ def : Pat<(fp_to_uint FPR32:$rs1), (FCVT
def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
} // Predicates = [HasStdExtF, IsRV32]
+
+let Predicates = [HasStdExtF, IsRV32] in {
+// FP->[u]int. Round-to-zero must be used
+def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
+def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
+} // Predicates = [HasStdExtF, IsRV32]
+
+let Predicates = [HasStdExtF, IsRV64] in {
+def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
+def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
+def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)),
+ (FMV_X_W FPR32:$src)>;
+
+// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
+// because fpto[u|s]i produces poison if the value can't fit into the target.
+// We match the single case below because fcvt.wu.s sign-extends its result so
+// is cheaper than fcvt.lu.s+sext.w.
+def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32),
+ (FCVT_WU_S $rs1, 0b001)>;
+
+// FP->[u]int64
+def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>;
+def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>;
+def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>;
+} // Predicates = [HasStdExtF, IsRV64]
Modified: llvm/trunk/test/CodeGen/RISCV/float-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-arith.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-arith.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-arith.ll Thu Jan 31 14:48:38 2019
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
@@ -14,6 +16,14 @@ define float @fadd_s(float %a, float %b)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
ret float %1
}
@@ -26,6 +36,14 @@ define float @fsub_s(float %a, float %b)
; RV32IF-NEXT: fsub.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fsub.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fsub float %a, %b
ret float %1
}
@@ -38,6 +56,14 @@ define float @fmul_s(float %a, float %b)
; RV32IF-NEXT: fmul.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmul_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmul.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fmul float %a, %b
ret float %1
}
@@ -50,6 +76,14 @@ define float @fdiv_s(float %a, float %b)
; RV32IF-NEXT: fdiv.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fdiv_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fdiv.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fdiv float %a, %b
ret float %1
}
@@ -63,6 +97,13 @@ define float @fsqrt_s(float %a) nounwind
; RV32IF-NEXT: fsqrt.s ft0, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsqrt_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fsqrt.s ft0, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.sqrt.f32(float %a)
ret float %1
}
@@ -77,6 +118,14 @@ define float @fsgnj_s(float %a, float %b
; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsgnj_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.copysign.f32(float %a, float %b)
ret float %1
}
@@ -91,6 +140,14 @@ define i32 @fneg_s(float %a, float %b) n
; RV32IF-NEXT: fneg.s ft1, ft0
; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fneg_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fadd.s ft0, ft0, ft0
+; RV64IF-NEXT: fneg.s ft1, ft0
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: ret
%1 = fadd float %a, %a
%2 = fneg float %1
%3 = fcmp oeq float %1, %2
@@ -109,6 +166,15 @@ define float @fsgnjn_s(float %a, float %
; RV32IF-NEXT: fsgnjn.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsgnjn_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = fneg float %1
%3 = call float @llvm.copysign.f32(float %a, float %2)
@@ -129,6 +195,16 @@ define float @fabs_s(float %a, float %b)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fabs_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fabs.s ft1, ft0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = call float @llvm.fabs.f32(float %1)
%3 = fadd float %2, %1
@@ -145,6 +221,14 @@ define float @fmin_s(float %a, float %b)
; RV32IF-NEXT: fmin.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmin_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmin.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.minnum.f32(float %a, float %b)
ret float %1
}
@@ -159,6 +243,14 @@ define float @fmax_s(float %a, float %b)
; RV32IF-NEXT: fmax.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmax_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmax.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %1
}
@@ -170,6 +262,13 @@ define i32 @feq_s(float %a, float %b) no
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: feq_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -182,6 +281,13 @@ define i32 @flt_s(float %a, float %b) no
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flt_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -194,6 +300,13 @@ define i32 @fle_s(float %a, float %b) no
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fle_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -210,6 +323,15 @@ define float @fmadd_s(float %a, float %b
; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1
}
@@ -227,6 +349,19 @@ define float @fmsub_s(float %a, float %b
; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: lui a2, %hi(.LCPI15_0)
+; RV64IF-NEXT: addi a2, a2, %lo(.LCPI15_0)
+; RV64IF-NEXT: flw ft1, 0(a2)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
%negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
@@ -247,6 +382,20 @@ define float @fnmadd_s(float %a, float %
; RV32IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fnmadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: lui a2, %hi(.LCPI16_0)
+; RV64IF-NEXT: addi a2, a2, %lo(.LCPI16_0)
+; RV64IF-NEXT: flw ft1, 0(a2)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fadd.s ft1, ft2, ft1
+; RV64IF-NEXT: fmv.w.x ft2, a1
+; RV64IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a
%c_ = fadd float 0.0, %c
%nega = fsub float -0.0, %a_
@@ -268,6 +417,19 @@ define float @fnmsub_s(float %a, float %
; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fnmsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
+; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; RV64IF-NEXT: flw ft1, 0(a0)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft1, a2
+; RV64IF-NEXT: fmv.w.x ft2, a1
+; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a
%nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
Modified: llvm/trunk/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll Thu Jan 31 14:48:38 2019
@@ -5,6 +5,8 @@
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
; This file tests cases where simple floating point operations can be
; profitably handled though bit manipulation if a soft-float ABI is being used
@@ -30,6 +32,12 @@ define float @fneg(float %a) nounwind {
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
+;
+; RV64IF-LABEL: fneg:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: lui a1, 524288
+; RV64IF-NEXT: xor a0, a0, a1
+; RV64IF-NEXT: ret
%1 = fneg float %a
ret float %1
}
@@ -57,6 +65,13 @@ define float @fabs(float %a) nounwind {
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
+;
+; RV64IF-LABEL: fabs:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: lui a1, 524288
+; RV64IF-NEXT: addiw a1, a1, -1
+; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: ret
%1 = call float @llvm.fabs.f32(float %a)
ret float %1
}
@@ -97,6 +112,14 @@ define float @fcopysign_fneg(float %a, f
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
+;
+; RV64IF-LABEL: fcopysign_fneg:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fneg float %b
%2 = call float @llvm.copysign.f32(float %a, float %1)
ret float %2
Modified: llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll Thu Jan 31 14:48:38 2019
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
declare void @abort()
declare void @exit(i32)
@@ -19,6 +21,19 @@ define void @br_fcmp_false(float %a, flo
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB0_2: # %if.else
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_false:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: addi a0, zero, 1
+; RV64IF-NEXT: bnez a0, .LBB0_2
+; RV64IF-NEXT: # %bb.1: # %if.then
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB0_2: # %if.else
+; RV64IF-NEXT: call abort
%1 = fcmp false float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -43,6 +58,21 @@ define void @br_fcmp_oeq(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB1_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_oeq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB1_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB1_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -71,6 +101,22 @@ define void @br_fcmp_oeq_alt(float %a, f
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB2_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_oeq_alt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: beqz a0, .LBB2_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB2_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -95,6 +141,21 @@ define void @br_fcmp_ogt(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB3_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ogt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB3_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB3_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -119,6 +180,21 @@ define void @br_fcmp_oge(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_oge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB4_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB4_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -143,6 +219,21 @@ define void @br_fcmp_olt(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB5_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_olt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB5_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB5_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -167,6 +258,21 @@ define void @br_fcmp_ole(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB6_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ole:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB6_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB6_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -199,6 +305,28 @@ define void @br_fcmp_one(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB7_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_one:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: feq.s a1, ft0, ft1
+; RV64IF-NEXT: not a1, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: bnez a0, .LBB7_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB7_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -227,6 +355,25 @@ define void @br_fcmp_ord(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB8_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ord:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft0
+; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB8_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB8_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -256,6 +403,26 @@ define void @br_fcmp_ueq(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ueq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: feq.s a2, ft1, ft1
+; RV64IF-NEXT: and a1, a2, a1
+; RV64IF-NEXT: seqz a1, a1
+; RV64IF-NEXT: or a0, a0, a1
+; RV64IF-NEXT: bnez a0, .LBB9_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB9_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -281,6 +448,22 @@ define void @br_fcmp_ugt(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB10_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ugt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB10_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB10_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -306,6 +489,22 @@ define void @br_fcmp_uge(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB11_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_uge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB11_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB11_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -331,6 +530,22 @@ define void @br_fcmp_ult(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ult:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB12_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB12_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -356,6 +571,22 @@ define void @br_fcmp_ule(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB13_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_ule:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB13_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB13_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -381,6 +612,22 @@ define void @br_fcmp_une(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_une:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB14_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB14_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -409,6 +656,24 @@ define void @br_fcmp_uno(float %a, float
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB15_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_uno:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft0
+; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: bnez a0, .LBB15_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB15_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -431,6 +696,19 @@ define void @br_fcmp_true(float %a, floa
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB16_2: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_true:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: addi a0, zero, 1
+; RV64IF-NEXT: bnez a0, .LBB16_2
+; RV64IF-NEXT: # %bb.1: # %if.else
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB16_2: # %if.then
+; RV64IF-NEXT: call abort
%1 = fcmp true float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -471,6 +749,38 @@ define i32 @br_fcmp_store_load_stack_slo
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB17_3: # %if.then
; RV32IF-NEXT: call abort
+;
+; RV64IF-LABEL: br_fcmp_store_load_stack_slot:
+; RV64IF: # %bb.0: # %entry
+; RV64IF-NEXT: addi sp, sp, -32
+; RV64IF-NEXT: sd ra, 24(sp)
+; RV64IF-NEXT: sd s1, 16(sp)
+; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
+; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; RV64IF-NEXT: flw ft0, 0(a0)
+; RV64IF-NEXT: fsw ft0, 12(sp)
+; RV64IF-NEXT: fmv.x.w s1, ft0
+; RV64IF-NEXT: mv a0, s1
+; RV64IF-NEXT: call dummy
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: flw ft1, 12(sp)
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: beqz a0, .LBB17_3
+; RV64IF-NEXT: # %bb.1: # %if.end
+; RV64IF-NEXT: mv a0, s1
+; RV64IF-NEXT: call dummy
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: flw ft1, 12(sp)
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: beqz a0, .LBB17_3
+; RV64IF-NEXT: # %bb.2: # %if.end4
+; RV64IF-NEXT: mv a0, zero
+; RV64IF-NEXT: ld s1, 16(sp)
+; RV64IF-NEXT: ld ra, 24(sp)
+; RV64IF-NEXT: addi sp, sp, 32
+; RV64IF-NEXT: ret
+; RV64IF-NEXT: .LBB17_3: # %if.then
+; RV64IF-NEXT: call abort
entry:
%call = call float @dummy(float 0.000000e+00)
%cmp = fcmp une float %call, 0.000000e+00
Modified: llvm/trunk/test/CodeGen/RISCV/float-convert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-convert.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-convert.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-convert.ll Thu Jan 31 14:48:38 2019
@@ -1,23 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
+; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
+; because fptosi will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_w_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_w_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: ret
%1 = fptosi float %a to i32
ret i32 %1
}
+; For RV64F, fcvt.lu.s is semantically equivalent to fcvt.wu.s in this case
+; because fptoui will produce poison if the result doesn't fit into an i32.
define i32 @fcvt_wu_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_wu_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: ret
%1 = fptoui float %a to i32
ret i32 %1
}
@@ -30,6 +48,14 @@ define i32 @fmv_x_w(float %a, float %b)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmv_x_w:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
; Ensure fmv.x.w is generated even for a soft float calling convention
%1 = fadd float %a, %b
%2 = bitcast float %1 to i32
@@ -42,6 +68,12 @@ define float @fcvt_s_w(i32 %a) nounwind
; RV32IF-NEXT: fcvt.s.w ft0, a0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_w:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.w ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = sitofp i32 %a to float
ret float %1
}
@@ -52,6 +84,12 @@ define float @fcvt_s_wu(i32 %a) nounwind
; RV32IF-NEXT: fcvt.s.wu ft0, a0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_wu:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = uitofp i32 %a to float
ret float %1
}
@@ -64,9 +102,93 @@ define float @fmv_w_x(i32 %a, i32 %b) no
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmv_w_x:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
; Ensure fmv.w.x is generated even for a soft float calling convention
%1 = bitcast i32 %a to float
%2 = bitcast i32 %b to float
%3 = fadd float %1, %2
ret float %3
}
+
+define i64 @fcvt_l_s(float %a) nounwind {
+; RV32IF-LABEL: fcvt_l_s:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: call __fixsfdi
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_l_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptosi float %a to i64
+ ret i64 %1
+}
+
+define i64 @fcvt_lu_s(float %a) nounwind {
+; RV32IF-LABEL: fcvt_lu_s:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: call __fixunssfdi
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_lu_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptoui float %a to i64
+ ret i64 %1
+}
+
+define float @fcvt_s_l(i64 %a) nounwind {
+; RV32IF-LABEL: fcvt_s_l:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: call __floatdisf
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_l:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.l ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = sitofp i64 %a to float
+ ret float %1
+}
+
+define float @fcvt_s_lu(i64 %a) nounwind {
+; RV32IF-LABEL: fcvt_s_lu:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: call __floatundisf
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcvt_s_lu:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.lu ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = uitofp i64 %a to float
+ ret float %1
+}
Modified: llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll Thu Jan 31 14:48:38 2019
@@ -1,12 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
define i32 @fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_false:
; RV32IF: # %bb.0:
; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_false:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: mv a0, zero
+; RV64IF-NEXT: ret
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -19,6 +26,13 @@ define i32 @fcmp_oeq(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_oeq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -31,6 +45,13 @@ define i32 @fcmp_ogt(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ogt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -43,6 +64,13 @@ define i32 @fcmp_oge(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_oge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -55,6 +83,13 @@ define i32 @fcmp_olt(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_olt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -67,6 +102,13 @@ define i32 @fcmp_ole(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ole:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -86,6 +128,20 @@ define i32 @fcmp_one(float %a, float %b)
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_one:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: feq.s a1, ft0, ft1
+; RV64IF-NEXT: not a1, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -102,6 +158,17 @@ define i32 @fcmp_ord(float %a, float %b)
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ord:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft0
+; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -119,6 +186,18 @@ define i32 @fcmp_ueq(float %a, float %b)
; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ueq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: feq.s a2, ft1, ft1
+; RV64IF-NEXT: and a1, a2, a1
+; RV64IF-NEXT: seqz a1, a1
+; RV64IF-NEXT: or a0, a0, a1
+; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -132,6 +211,14 @@ define i32 @fcmp_ugt(float %a, float %b)
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ugt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -145,6 +232,14 @@ define i32 @fcmp_uge(float %a, float %b)
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_uge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -158,6 +253,14 @@ define i32 @fcmp_ult(float %a, float %b)
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ult:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -171,6 +274,14 @@ define i32 @fcmp_ule(float %a, float %b)
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_ule:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -184,6 +295,14 @@ define i32 @fcmp_une(float %a, float %b)
; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_une:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: ret
%1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -199,6 +318,16 @@ define i32 @fcmp_uno(float %a, float %b)
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_uno:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft0
+; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -209,6 +338,11 @@ define i32 @fcmp_true(float %a, float %b
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fcmp_true:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi a0, zero, 1
+; RV64IF-NEXT: ret
%1 = fcmp true float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Modified: llvm/trunk/test/CodeGen/RISCV/float-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-imm.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-imm.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-imm.ll Thu Jan 31 14:48:38 2019
@@ -1,13 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
+; TODO: constant pool shouldn't be necessary for RV64IF.
define float @float_imm() nounwind {
; RV32IF-LABEL: float_imm:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, 263313
; RV32IF-NEXT: addi a0, a0, -37
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: float_imm:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: lui a0, %hi(.LCPI0_0)
+; RV64IF-NEXT: addi a0, a0, %lo(.LCPI0_0)
+; RV64IF-NEXT: flw ft0, 0(a0)
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
ret float 3.14159274101257324218750
}
@@ -22,6 +33,16 @@ define float @float_imm_op(float %a) nou
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: float_imm_op:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
+; RV64IF-NEXT: addi a0, a0, %lo(.LCPI1_0)
+; RV64IF-NEXT: flw ft1, 0(a0)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
}
Modified: llvm/trunk/test/CodeGen/RISCV/float-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-mem.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-mem.ll Thu Jan 31 14:48:38 2019
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
define float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw:
@@ -10,6 +12,14 @@ define float @flw(float *%a) nounwind {
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flw:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: flw ft0, 12(a0)
+; RV64IF-NEXT: flw ft1, 0(a0)
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3
%3 = load float, float* %2
@@ -30,6 +40,15 @@ define void @fsw(float *%a, float %b, fl
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: fsw ft0, 0(a0)
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsw:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fsw ft0, 32(a0)
+; RV64IF-NEXT: fsw ft0, 0(a0)
+; RV64IF-NEXT: ret
%1 = fadd float %b, %c
store float %1, float* %a
%2 = getelementptr float, float* %a, i32 8
@@ -56,6 +75,20 @@ define float @flw_fsw_global(float %a, f
; RV32IF-NEXT: fsw ft0, 36(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flw_fsw_global:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: lui a0, %hi(G)
+; RV64IF-NEXT: flw ft1, %lo(G)(a0)
+; RV64IF-NEXT: fsw ft0, %lo(G)(a0)
+; RV64IF-NEXT: addi a0, a0, %lo(G)
+; RV64IF-NEXT: flw ft1, 36(a0)
+; RV64IF-NEXT: fsw ft0, 36(a0)
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = load volatile float, float* @G
store float %1, float* @G
@@ -76,6 +109,18 @@ define float @flw_fsw_constant(float %a)
; RV32IF-NEXT: fsw ft0, -273(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flw_fsw_constant:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: lui a0, 56
+; RV64IF-NEXT: addiw a0, a0, -1353
+; RV64IF-NEXT: slli a0, a0, 14
+; RV64IF-NEXT: flw ft1, -273(a0)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fsw ft0, -273(a0)
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = inttoptr i32 3735928559 to float*
%2 = load volatile float, float* %1
%3 = fadd float %a, %2
@@ -102,6 +147,23 @@ define float @flw_stack(float %a) nounwi
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flw_stack:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -32
+; RV64IF-NEXT: sd ra, 24(sp)
+; RV64IF-NEXT: sd s1, 16(sp)
+; RV64IF-NEXT: mv s1, a0
+; RV64IF-NEXT: addi a0, sp, 12
+; RV64IF-NEXT: call notdead
+; RV64IF-NEXT: fmv.w.x ft0, s1
+; RV64IF-NEXT: flw ft1, 12(sp)
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ld s1, 16(sp)
+; RV64IF-NEXT: ld ra, 24(sp)
+; RV64IF-NEXT: addi sp, sp, 32
+; RV64IF-NEXT: ret
%1 = alloca float, align 4
%2 = bitcast float* %1 to i8*
call void @notdead(i8* %2)
@@ -124,6 +186,20 @@ define void @fsw_stack(float %a, float %
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsw_stack:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fsw ft0, 4(sp)
+; RV64IF-NEXT: addi a0, sp, 4
+; RV64IF-NEXT: call notdead
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b ; force store from FPR32
%2 = alloca float, align 4
store float %1, float* %2
Modified: llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll?rev=352807&r1=352806&r2=352807&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll Thu Jan 31 14:48:38 2019
@@ -1,12 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
define float @select_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: select_fcmp_false:
; RV32IF: # %bb.0:
; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_false:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: mv a0, a1
+; RV64IF-NEXT: ret
%1 = fcmp false float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -24,6 +31,18 @@ define float @select_fcmp_oeq(float %a,
; RV32IF-NEXT: .LBB1_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_oeq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: bnez a0, .LBB1_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB1_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -41,6 +60,18 @@ define float @select_fcmp_ogt(float %a,
; RV32IF-NEXT: .LBB2_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ogt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB2_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB2_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ogt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -58,6 +89,18 @@ define float @select_fcmp_oge(float %a,
; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_oge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB3_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB3_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oge float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -75,6 +118,18 @@ define float @select_fcmp_olt(float %a,
; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_olt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: flt.s a0, ft0, ft1
+; RV64IF-NEXT: bnez a0, .LBB4_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB4_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -92,6 +147,18 @@ define float @select_fcmp_ole(float %a,
; RV32IF-NEXT: .LBB5_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ole:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fle.s a0, ft0, ft1
+; RV64IF-NEXT: bnez a0, .LBB5_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB5_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -117,6 +184,25 @@ define float @select_fcmp_one(float %a,
; RV32IF-NEXT: .LBB6_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_one:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: feq.s a1, ft0, ft1
+; RV64IF-NEXT: not a1, a1
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: bnez a0, .LBB6_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB6_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -138,6 +224,22 @@ define float @select_fcmp_ord(float %a,
; RV32IF-NEXT: .LBB7_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ord:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB7_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB7_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -160,6 +262,23 @@ define float @select_fcmp_ueq(float %a,
; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ueq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: feq.s a1, ft0, ft1
+; RV64IF-NEXT: or a0, a1, a0
+; RV64IF-NEXT: bnez a0, .LBB8_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB8_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -178,6 +297,19 @@ define float @select_fcmp_ugt(float %a,
; RV32IF-NEXT: .LBB9_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ugt:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fle.s a0, ft0, ft1
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB9_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB9_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ugt float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -196,6 +328,19 @@ define float @select_fcmp_uge(float %a,
; RV32IF-NEXT: .LBB10_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_uge:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: flt.s a0, ft0, ft1
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB10_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB10_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp uge float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -214,6 +359,19 @@ define float @select_fcmp_ult(float %a,
; RV32IF-NEXT: .LBB11_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ult:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB11_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB11_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ult float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -232,6 +390,19 @@ define float @select_fcmp_ule(float %a,
; RV32IF-NEXT: .LBB12_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_ule:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB12_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB12_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ule float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -250,6 +421,19 @@ define float @select_fcmp_une(float %a,
; RV32IF-NEXT: .LBB13_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_une:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: xori a0, a0, 1
+; RV64IF-NEXT: bnez a0, .LBB13_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB13_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp une float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -271,6 +455,21 @@ define float @select_fcmp_uno(float %a,
; RV32IF-NEXT: .LBB14_2:
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_uno:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: feq.s a0, ft1, ft1
+; RV64IF-NEXT: feq.s a1, ft0, ft0
+; RV64IF-NEXT: and a0, a1, a0
+; RV64IF-NEXT: seqz a0, a0
+; RV64IF-NEXT: bnez a0, .LBB14_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: fmv.s ft0, ft1
+; RV64IF-NEXT: .LBB14_2:
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -280,6 +479,10 @@ define float @select_fcmp_true(float %a,
; RV32IF-LABEL: select_fcmp_true:
; RV32IF: # %bb.0:
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: select_fcmp_true:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: ret
%1 = fcmp true float %a, %b
%2 = select i1 %1, float %a, float %b
ret float %2
@@ -298,6 +501,18 @@ define i32 @i32_select_fcmp_oeq(float %a
; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: mv a0, a2
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: i32_select_fcmp_oeq:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: bnez a0, .LBB16_2
+; RV64IF-NEXT: # %bb.1:
+; RV64IF-NEXT: mv a2, a3
+; RV64IF-NEXT: .LBB16_2:
+; RV64IF-NEXT: mv a0, a2
+; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
Added: llvm/trunk/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll?rev=352807&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll Thu Jan 31 14:48:38 2019
@@ -0,0 +1,86 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
+
+; This file provides a simple sanity check of float and double operations for
+; RV32I and RV64I. This is primarily intended to ensure that custom
+; legalisation or DAG combines aren't incorrectly triggered when the F
+; extension isn't enabled.
+
+; TODO: f32 parameters on RV64 with a soft-float ABI are anyext.
+
+define float @float_test(float %a, float %b) nounwind {
+; RV32IF-LABEL: float_test:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: sw s1, 8(sp)
+; RV32IF-NEXT: mv s1, a1
+; RV32IF-NEXT: call __addsf3
+; RV32IF-NEXT: mv a1, s1
+; RV32IF-NEXT: call __divsf3
+; RV32IF-NEXT: lw s1, 8(sp)
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: float_test:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: sd s1, 0(sp)
+; RV64IF-NEXT: slli a0, a0, 32
+; RV64IF-NEXT: srli a0, a0, 32
+; RV64IF-NEXT: slli a1, a1, 32
+; RV64IF-NEXT: srli s1, a1, 32
+; RV64IF-NEXT: mv a1, s1
+; RV64IF-NEXT: call __addsf3
+; RV64IF-NEXT: mv a1, s1
+; RV64IF-NEXT: call __divsf3
+; RV64IF-NEXT: ld s1, 0(sp)
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+ %1 = fadd float %a, %b
+ %2 = fdiv float %1, %b
+ ret float %2
+}
+
+define double @double_test(double %a, double %b) nounwind {
+; RV32IF-LABEL: double_test:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: sw s1, 8(sp)
+; RV32IF-NEXT: sw s2, 4(sp)
+; RV32IF-NEXT: mv s2, a3
+; RV32IF-NEXT: mv s1, a2
+; RV32IF-NEXT: call __adddf3
+; RV32IF-NEXT: mv a2, s1
+; RV32IF-NEXT: mv a3, s2
+; RV32IF-NEXT: call __divdf3
+; RV32IF-NEXT: lw s2, 4(sp)
+; RV32IF-NEXT: lw s1, 8(sp)
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: double_test:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: addi sp, sp, -16
+; RV64IF-NEXT: sd ra, 8(sp)
+; RV64IF-NEXT: sd s1, 0(sp)
+; RV64IF-NEXT: mv s1, a1
+; RV64IF-NEXT: call __adddf3
+; RV64IF-NEXT: mv a1, s1
+; RV64IF-NEXT: call __divdf3
+; RV64IF-NEXT: ld s1, 0(sp)
+; RV64IF-NEXT: ld ra, 8(sp)
+; RV64IF-NEXT: addi sp, sp, 16
+; RV64IF-NEXT: ret
+ %1 = fadd double %a, %b
+ %2 = fdiv double %1, %b
+ ret double %2
+}
Added: llvm/trunk/test/CodeGen/RISCV/rv64f-float-convert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/rv64f-float-convert.ll?rev=352807&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/rv64f-float-convert.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/rv64f-float-convert.ll Thu Jan 31 14:48:38 2019
@@ -0,0 +1,187 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IF
+
+; This file exhaustively checks float<->i32 conversions. In general,
+; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
+; generated for an fpto[s|u]i conversion if the result doesn't fit in the
+; target type.
+
+define i32 @aext_fptosi(float %a) nounwind {
+; RV64IF-LABEL: aext_fptosi:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptosi float %a to i32
+ ret i32 %1
+}
+
+define signext i32 @sext_fptosi(float %a) nounwind {
+; RV64IF-LABEL: sext_fptosi:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptosi float %a to i32
+ ret i32 %1
+}
+
+define zeroext i32 @zext_fptosi(float %a) nounwind {
+; RV64IF-LABEL: zext_fptosi:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: slli a0, a0, 32
+; RV64IF-NEXT: srli a0, a0, 32
+; RV64IF-NEXT: ret
+ %1 = fptosi float %a to i32
+ ret i32 %1
+}
+
+define i32 @aext_fptoui(float %a) nounwind {
+; RV64IF-LABEL: aext_fptoui:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptoui float %a to i32
+ ret i32 %1
+}
+
+define signext i32 @sext_fptoui(float %a) nounwind {
+; RV64IF-LABEL: sext_fptoui:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptoui float %a to i32
+ ret i32 %1
+}
+
+define zeroext i32 @zext_fptoui(float %a) nounwind {
+; RV64IF-LABEL: zext_fptoui:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT: ret
+ %1 = fptoui float %a to i32
+ ret i32 %1
+}
+
+define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
+; RV64IF-LABEL: bcvt_f32_to_aext_i32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = fadd float %a, %b
+ %2 = bitcast float %1 to i32
+ ret i32 %2
+}
+
+define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
+; RV64IF-LABEL: bcvt_f32_to_sext_i32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = fadd float %a, %b
+ %2 = bitcast float %1 to i32
+ ret i32 %2
+}
+
+define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
+; RV64IF-LABEL: bcvt_f32_to_zext_i32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: slli a0, a0, 32
+; RV64IF-NEXT: srli a0, a0, 32
+; RV64IF-NEXT: ret
+ %1 = fadd float %a, %b
+ %2 = bitcast float %1 to i32
+ ret i32 %2
+}
+
+define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
+; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = trunc i64 %a to i32
+ %2 = trunc i64 %b to i32
+ %3 = bitcast i32 %1 to float
+ %4 = bitcast i32 %2 to float
+ %5 = fadd float %3, %4
+ ret float %5
+}
+
+define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
+; RV64IF-LABEL: uitofp_aext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = uitofp i32 %a to float
+ ret float %1
+}
+
+define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
+; RV64IF-LABEL: uitofp_sext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = uitofp i32 %a to float
+ ret float %1
+}
+
+define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
+; RV64IF-LABEL: uitofp_zext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.wu ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = uitofp i32 %a to float
+ ret float %1
+}
+
+define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
+; RV64IF-LABEL: sitofp_aext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.w ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = sitofp i32 %a to float
+ ret float %1
+}
+
+define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
+; RV64IF-LABEL: sitofp_sext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.l ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = sitofp i32 %a to float
+ ret float %1
+}
+
+define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
+; RV64IF-LABEL: sitofp_zext_i32_to_f32:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fcvt.s.w ft0, a0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
+ %1 = sitofp i32 %a to float
+ ret float %1
+}
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