[PATCH] D57491: [DAGCombine] Avoid CombineZExtLogicopShiftLoad if there is free ZEXT
Guozhi Wei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 31 12:46:56 PST 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL352792: [DAGCombine] Avoid CombineZExtLogicopShiftLoad if there is free ZEXT (authored by Carrot, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D57491?vs=184519&id=184580#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D57491/new/
https://reviews.llvm.org/D57491
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/pr39098.ll
Index: llvm/trunk/test/CodeGen/X86/pr39098.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr39098.ll
+++ llvm/trunk/test/CodeGen/X86/pr39098.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define dso_local void @test_cancel2(i40* %p1, i40* %p2) {
+; CHECK: # %entry
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: shrl %eax
+; CHECK-NEXT: andl $524287, %eax
+; CHECK-NEXT: movl %eax, (%rsi)
+; CHECK-NEXT: movb $0, 4(%rsi)
+; CHECK-NEXT: retq
+entry:
+ %0 = load i40, i40* %p1, align 8
+ %shl414 = shl i40 %0, 19
+ %unsclear415 = and i40 %shl414, 549755813887
+ %shr416 = lshr i40 %unsclear415, 20
+ %unsclear417 = and i40 %shr416, 549755813887
+ store i40 %unsclear417, i40* %p2, align 8
+ ret void
+}
+
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8402,6 +8402,9 @@
SDValue DAGCombiner::CombineZExtLogicopShiftLoad(SDNode *N) {
assert(N->getOpcode() == ISD::ZERO_EXTEND);
EVT VT = N->getValueType(0);
+ EVT OrigVT = N->getOperand(0).getValueType();
+ if (TLI.isZExtFree(OrigVT, VT))
+ return SDValue();
// and/or/xor
SDValue N0 = N->getOperand(0);
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