[PATCH] D53235: [RISCV] Add RV64F codegen support

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

LGTM

Making FMV_X_ANYEXTW_RV64 any-extend the result seems fine.



================
Comment at: lib/Target/RISCV/RISCVInstrInfoF.td:372
+def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR32:$rs1)), i32),
+          (FCVT_WU_S $rs1, 0b001)>;
+
----------------
This is supposed to be assertzexti32, as opposed to zexti32, right?  I doubt it has any practical impact because an "AND" would be dead, but better to be clear.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235