[PATCH] D57504: RFC: EVL Prototype & Roadmap for vector predication in LLVM

[Simon Moll via Phabricator via llvm-commits]

simoll created this revision.
Herald added subscribers: llvm-commits, PkmX, dexonsmith, rogfer01, steven_wu, bollu, kristof.beyls, javed.absar, mgorny, mehdi_amini.

This proposal defines a roadmap towards native vector predication in LLVM, specifically for vector instructions with a mask and/or an explicit vector length.
LLVM currently has no target-independent means to model predicated vector instructions for modern SIMD ISAs such as AVX512, ARM SVE, the RISC-V V extension and NEC SX-Aurora.
Only some predicated vector operations, such as masked loads and stores are available through intrinsics [MaskedIR]_.

Please use `docs/Proposals/VectorPredication.rst` to comment on the summary.

The Explicit Vector Length extension
====================================

The Explicit Vector Length (EVL) extension [EvlRFC]_ can be a first step towards native vector predication.
The EVL prototype in this patch demonstrates the following concepts:

- Predicated vector intrinsics with an explicit mask and vector length parameter on IR level.
- First-class predicated SDNodes on ISel level. Mask and vector length are value operands.
- An incremental strategy to generalize PatternMatch/InstCombine/InstSimplify and DAGCombiner to work on both regular instructions and EVL intrinsics.
- DAGCombiner example: FMA fusion.
- InstCombine/InstSimplify example: FSub pattern re-writes.
- Early experiments on the LNT test suite (Clang static release, `O3 -ffast-math`) indicate that compile time on non-EVL IR is not affected by the API abstractions in PatternMatch, etc.

Roadmap
=======

Drawing from the EVL prototype, we propose the following roadmap towards native vector predication in LLVM:

**1. IR-level EVL intrinsics**

- There is a consensus on the semantics/instruction set of EVL.
- EVL intrinsics and attributes are available on IR level.
- TTI has capability flags for EVL (``supportsEVL()``?, ``haveActiveVectorLength()``?).

Result: EVL usable for IR-level vectorizers (LV, VPlan, RegionVectorizer), potential integration in Clang with builtins.

**2. CodeGen support**

- EVL intrinsics translate to first-class SDNodes (``llvm.evl.fdiv.* -> evl_fdiv``).
- EVL legalization (legalize explicit vector length to mask (AVX512), legalize EVL SDNodes to pre-existing ones (SSE, NEON)).

Result: Backend development based on EVL SDNodes.

**3. Lift InstSimplify/InstCombine/DAGCombiner to EVL**

- Introduce PredicatedInstruction, PredicatedBinaryOperator, .. helper classes that match standard vector IR and EVL intrinsics.
- Add a matcher context to PatternMatch and context-aware IR Builder APIs.
- Incrementally lift DAGCombiner to work on EVL SDNodes as well as on regular vector instructions.
- Incrementally lift InstCombine/InstSimplify to operate on EVL as well as regular IR instructions.

Result: Optimization of EVL intrinsics on par with standard vector instructions.

**4. Deprecate llvm.masked.* / llvm.experimental.reduce.***

- Modernize llvm.masked.* / llvm.experimental.reduce* by translating to EVL.
- DCE transitional APIs.

Result: EVL has superseded earlier vector intrinsics.

**5. Predicated IR Instructions**

- Vector instructions have an optional mask and vector length parameter. These lower to EVL SDNodes (from Stage 2).
- Phase out EVL intrinsics, only keeping those that are not equivalent to vectorized scalar instructions (reduce,
- InstCombine/InstSimplify expect predication in regular Instructions (Stage (3) has laid the groundwork).

shuffles, ..).

Result: Native vector predication in IR.

References
==========

.. [MaskedIR] `llvm.masked.*` intrinsics, https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics
.. [EvlRFC] Explicit Vector Length RFC, https://reviews.llvm.org/D53613


Repository:
  rL LLVM

https://reviews.llvm.org/D57504

Files:
  docs/Proposals/VectorPredication.rst
  include/llvm/Analysis/InstructionSimplify.h
  include/llvm/Bitcode/LLVMBitCodes.h
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/CodeGen/SelectionDAGNodes.h
  include/llvm/IR/Attributes.td
  include/llvm/IR/EVLBuilder.h
  include/llvm/IR/InstrTypes.h
  include/llvm/IR/IntrinsicInst.h
  include/llvm/IR/Intrinsics.td
  include/llvm/IR/MatcherCast.h
  include/llvm/IR/PatternMatch.h
  include/llvm/IR/PredicatedInst.h
  include/llvm/Target/TargetSelectionDAG.td
  lib/Analysis/InstructionSimplify.cpp
  lib/AsmParser/LLLexer.cpp
  lib/AsmParser/LLParser.cpp
  lib/AsmParser/LLToken.h
  lib/Bitcode/Reader/BitcodeReader.cpp
  lib/Bitcode/Writer/BitcodeWriter.cpp
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  lib/IR/Attributes.cpp
  lib/IR/CMakeLists.txt
  lib/IR/EVLBuilder.cpp
  lib/IR/IntrinsicInst.cpp
  lib/IR/PredicatedInst.cpp
  lib/IR/Verifier.cpp
  lib/Transforms/InstCombine/InstCombineAddSub.cpp
  lib/Transforms/InstCombine/InstCombineCalls.cpp
  lib/Transforms/InstCombine/InstCombineInternal.h
  lib/Transforms/Utils/CodeExtractor.cpp
  test/Bitcode/attributes.ll
  test/Transforms/InstCombine/evl-fsub.ll
  test/Transforms/InstSimplify/evl-fsub.ll
  test/Verifier/evl_attribs.ll
  utils/TableGen/CodeGenIntrinsics.h
  utils/TableGen/CodeGenTarget.cpp
  utils/TableGen/IntrinsicEmitter.cpp

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