[PATCH] D53235: [RISCV] Add RV64F codegen support

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:666
+    if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64)
+      return DCI.CombineTo(N, Op0.getOperand(0));
+
----------------
This combine isn't consistent with the ComputeNumSignBitsForTargetNode change: if value is supposed to be sign-extended, you need to insert a SIGN_EXTEND_INREG


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235