[PATCH] D57389: [X86] Improve use of SHLD/SHRD

Amaury SECHET via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 29 17:24:58 PST 2019


deadalnix marked 2 inline comments as done.
deadalnix added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:37020
     ShAmt1 = ShAmt1.getOperand(0);
   }
 
----------------
The operation is similar to what's done here.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:37054
+        ShAmt1Op1 = ShAmt1Op1.getOperand(0);
+      }
       if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
----------------
RKSimon wrote:
> Maybe use DAG.GetDemandedBits ?
It's not obvious to me that it would work. The and opcode itself uses it, so there is no need to redo it here. We also need to know if masking took place to know what we can accept as LHS for the sub opcode.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57389/new/

https://reviews.llvm.org/D57389





More information about the llvm-commits mailing list