[PATCH] D57148: [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 184062.
andreadb marked an inline comment as done.
andreadb added a comment.

Patch updated.

I verified that the int-to-fp convert latency is 4cy (instead of 3cy) if we exclude the extra 6cy of bypass delay.
So, I went ahead and set the latency directly to 4cy.

I've also verified by running some microbenchmarks that the RM variants have a latency of ~9cy (5cy for the load opcode + 4cy of convert). That latency seems consistent with what I found when testing the RR variants. The only difference for the RM variants is the number of opcodes (it is 1 COP instead of 2 COPs).
So, I went ahead and fixed all those writes in this patch (rather than splitting the change in two patches).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57148/new/

https://reviews.llvm.org/D57148

Files:
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s
  test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse2.s

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