[PATCH] D57367: [DAGCombine] Do several rounds of combine for nodes using SimplifyDemandedBits.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix created this revision.
deadalnix added reviewers: arsenm, hfinkel, baldrick, efriedma, RKSimon, craig.topper, niravd, xbolva00.
Herald added a subscriber: wdng.

SimplifyDemandedBits can explore severallevels of the DAG docompute its result. This means that a transformation in the DAG that isn't immediately related to a node might affect it.

We therefore add these nodes to the DeepPatternNodes set so that they can be processed again in case the DAG is modfied.

In the future, other node may be added to the set as need arises.

This is a variation on D33587 <https://reviews.llvm.org/D33587> that should be more lightweight as it focuses the extra work on node that are actually likely to benefit from it rather than the whole DAG.


Repository:
  rL LLVM

https://reviews.llvm.org/D57367

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  test/CodeGen/X86/bypass-slow-division-32.ll
  test/CodeGen/X86/combine-fcopysign.ll
  test/CodeGen/X86/combine-srem.ll
  test/CodeGen/X86/constant-combines.ll
  test/CodeGen/X86/illegal-bitfield-loadstore.ll
  test/CodeGen/X86/jump_sign.ll
  test/CodeGen/X86/legalize-shift-64.ll
  test/CodeGen/X86/movmsk.ll
  test/CodeGen/X86/not-and-simplify.ll
  test/CodeGen/X86/pr32282.ll
  test/CodeGen/X86/pr33844.ll
  test/CodeGen/X86/pr35765.ll
  test/CodeGen/X86/pr38185.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/shift-double-x86_64.ll
  test/CodeGen/X86/shift-double.ll
  test/CodeGen/X86/uadd_sat_vec.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-sext-widen.ll
  test/CodeGen/X86/vector-sext.ll
  test/CodeGen/X86/vector-trunc-packus-widen.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat-widen.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-truncate-combine.ll
  test/CodeGen/X86/xor.ll

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