[llvm] r352437 - [CGP] auto-generate complete checks for add overflow tests; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 28 14:07:37 PST 2019
Author: spatel
Date: Mon Jan 28 14:07:37 2019
New Revision: 352437
URL: http://llvm.org/viewvc/llvm-project?rev=352437&view=rev
Log:
[CGP] auto-generate complete checks for add overflow tests; NFC
Modified:
llvm/trunk/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
Modified: llvm/trunk/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll?rev=352437&r1=352436&r2=352437&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll (original)
+++ llvm/trunk/test/Transforms/CodeGenPrepare/overflow-intrinsics.ll Mon Jan 28 14:07:37 2019
@@ -4,75 +4,101 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
-; CHECK-LABEL: @test1(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
define i64 @test1(i64 %a, i64 %b) nounwind ssp {
-entry:
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
+; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
+; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
+; CHECK-NEXT: ret i64 [[Q]]
+;
%add = add i64 %b, %a
%cmp = icmp ult i64 %add, %a
%Q = select i1 %cmp, i64 %b, i64 42
ret i64 %Q
}
-; CHECK-LABEL: @test2(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
define i64 @test2(i64 %a, i64 %b) nounwind ssp {
-entry:
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
+; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
+; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
+; CHECK-NEXT: ret i64 [[Q]]
+;
%add = add i64 %b, %a
%cmp = icmp ult i64 %add, %b
%Q = select i1 %cmp, i64 %b, i64 42
ret i64 %Q
}
-; CHECK-LABEL: @test3(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: ret i64
define i64 @test3(i64 %a, i64 %b) nounwind ssp {
-entry:
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
+; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
+; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
+; CHECK-NEXT: ret i64 [[Q]]
+;
%add = add i64 %b, %a
%cmp = icmp ugt i64 %b, %add
%Q = select i1 %cmp, i64 %b, i64 42
ret i64 %Q
}
-; CHECK-LABEL: @test4(
-; CHECK: llvm.uadd.with.overflow
-; CHECK: extractvalue
-; CHECK: extractvalue
-; CHECK: select
define i64 @test4(i64 %a, i64 %b, i1 %c) nounwind ssp {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C:%.*]], label [[NEXT:%.*]], label [[EXIT:%.*]]
+; CHECK: next:
+; CHECK-NEXT: [[UADD_OVERFLOW:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[B:%.*]], i64 [[A:%.*]])
+; CHECK-NEXT: [[UADD:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 0
+; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[UADD_OVERFLOW]], 1
+; CHECK-NEXT: [[Q:%.*]] = select i1 [[OVERFLOW]], i64 [[B]], i64 42
+; CHECK-NEXT: ret i64 [[Q]]
+; CHECK: exit:
+; CHECK-NEXT: ret i64 0
+;
entry:
%add = add i64 %b, %a
%cmp = icmp ugt i64 %b, %add
br i1 %c, label %next, label %exit
- next:
+next:
%Q = select i1 %cmp, i64 %b, i64 42
ret i64 %Q
- exit:
+exit:
ret i64 0
}
-; CHECK-LABEL: @test5(
-; CHECK-NOT: llvm.uadd.with.overflow
-; CHECK: next
define i64 @test5(i64 %a, i64 %b, i64* %ptr, i1 %c) nounwind ssp {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD:%.*]] = add i64 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: store i64 [[ADD]], i64* [[PTR:%.*]]
+; CHECK-NEXT: br i1 [[C:%.*]], label [[NEXT:%.*]], label [[EXIT:%.*]]
+; CHECK: next:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[B]], [[ADD]]
+; CHECK-NEXT: [[Q:%.*]] = select i1 [[TMP0]], i64 [[B]], i64 42
+; CHECK-NEXT: ret i64 [[Q]]
+; CHECK: exit:
+; CHECK-NEXT: ret i64 0
+;
entry:
%add = add i64 %b, %a
store i64 %add, i64* %ptr
%cmp = icmp ugt i64 %b, %add
br i1 %c, label %next, label %exit
- next:
+next:
%Q = select i1 %cmp, i64 %b, i64 42
ret i64 %Q
- exit:
+exit:
ret i64 0
}
; Check that every instruction inserted by -codegenprepare has a debug location.
; DEBUG: CheckModuleDebugify: PASS
+
More information about the llvm-commits
mailing list