[PATCH] D57298: [X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Assuming we don't insert emms implicitly, I'm not sure how to express the restriction at the IR level.

We could try to model the FP status register as "memory", somehow, and say every MMX operation writes to it, by marking them inaccessiblememonly or something like that.  But it's not clear how you model the interaction between that, and FP operations which we don't model as reading/writing memory.  Granted, if your MMX-using function doesn't contain any values of floating-point type, the result would mostly work in practice.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D57298/new/

https://reviews.llvm.org/D57298