[PATCH] D57029: GlobalISel: Fix narrowScalar for load/store with different mem size

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D57029#1373957 <https://reviews.llvm.org/D57029#1373957>, @aemerson wrote:

> In what situations can these kinds of loads be generated?
>
> At least for AArch64, the extending loads combiner only runs before legalisation, so it wouldn't have a chance to combine these. In the absence of a G_ANYEXTLOAD opcode, I think having an explicit G_ZEXTLOAD is preferable here even though it's slightly pessimistic.
>
> @dsanders thoughts?


I'm operating under the assumption that eventually we'll have canonicalizations that look like what SelectionDAG does today, which involves producing extloads like this.

On AMDGPU in some cases on some sub targets, there is a codegen difference between zextload and aextload so I think we should have a way to distinguish these. The current apparent representation choice I think is bug prone. I have a few patches I haven't posted yet fixing legalization bugs from inconsistently assuming the result size is the same as the memory size.


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