[llvm] r352303 - [X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce SUBREG_TO_REG

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Jan 26 19:37:05 2019
New Revision: 352303

URL: http://llvm.org/viewvc/llvm-project?rev=352303&view=rev
Log:
[X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce SUBREG_TO_REG

def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes.

Spotted in the diffs from D33587.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=352303&r1=352302&r2=352303&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sat Jan 26 19:37:05 2019
@@ -1350,6 +1350,8 @@ def def32 : PatLeaf<(i32 GR32:$src), [{
 // we can use a SUBREG_TO_REG.
 def : Pat<(i64 (zext def32:$src)),
           (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
+def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),
+          (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
 
 //===----------------------------------------------------------------------===//
 // Pattern match OR as ADD

Modified: llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.ll?rev=352303&r1=352302&r2=352303&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.ll (original)
+++ llvm/trunk/test/CodeGen/X86/zext-logicop-shift-load.ll Sat Jan 26 19:37:05 2019
@@ -103,7 +103,6 @@ define i64 @test8(i8* %data) {
 ; CHECK-NEXT:    movzwl %ax, %eax
 ; CHECK-NEXT:    shrl $2, %eax
 ; CHECK-NEXT:    orl $60, %eax
-; CHECK-NEXT:    movl %eax, %eax
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i8, i8* %data, align 4