[PATCH] D33587: [DAGCombine] Do several rounds of combine.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix updated this revision to Diff 183737.
deadalnix added a comment.

I'd like to ressurect this diff.

To me, it seems like the proper thing to do, at least at some optimisation level. As long as there are combine to do that we know how to do, we should be doign them.

I see a lot of people doing more and more clever pattern over time that are just not necessary as they are combinations of simpler patterns. This is a losing battle anyways because there is a combinatorial explosion. In addition, there are just many patterns that are just not very useful in isolation, but useful to put things in a canonical form that can be picked up later on. These types of transformations are not beneficial right now unless very simple.

I was able to write variosu patches that leverage this canonicalisation mechanism ad get great result for the uses cases I'm interested in (mostly cryptography, which involve a lot of big integer manipulation). I'm sure people interested in the performance of other type of code will find it beneficial as well. Ultimately I could do without this patch, but at the end, the alternative boils down to do something similar in specific cases - the ones I care about - instead of all cases, which seems like a big missed opportunity.

The results are better in numerous cases, terrific in some and there are little regressions in term of codegen quality. I'm happy to work on these regressions, but I'd like to ensure I'm not wasting my time if that patch has no chances to get in.

TL;DR: Not doing this is creating work and complexity in addition to making it prohibitively complex to do some optimisations. I think we should do this, at higher optimisation levels such as O2 <https://reviews.llvm.org/owners/package/2/>/O3 <https://reviews.llvm.org/owners/package/3/>.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D33587/new/

https://reviews.llvm.org/D33587

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/aligned-variadic.ll
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/avx-load-store.ll
  test/CodeGen/X86/avx512-any_extend_load.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512-mask-op.ll
  test/CodeGen/X86/bypass-slow-division-32.ll
  test/CodeGen/X86/combine-fcopysign.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-srem.ll
  test/CodeGen/X86/constant-combines.ll
  test/CodeGen/X86/extract-insert.ll
  test/CodeGen/X86/illegal-bitfield-loadstore.ll
  test/CodeGen/X86/insertelement-ones.ll
  test/CodeGen/X86/jump_sign.ll
  test/CodeGen/X86/legalize-shift-64.ll
  test/CodeGen/X86/mmx-cvt.ll
  test/CodeGen/X86/movmsk.ll
  test/CodeGen/X86/not-and-simplify.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/pr32282.ll
  test/CodeGen/X86/pr33844.ll
  test/CodeGen/X86/pr34592.ll
  test/CodeGen/X86/pr35765.ll
  test/CodeGen/X86/pr38185.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/shift-double-x86_64.ll
  test/CodeGen/X86/shift-double.ll
  test/CodeGen/X86/sse3.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
  test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
  test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
  test/CodeGen/X86/usub_sat_vec.ll
  test/CodeGen/X86/vec_extract-mmx.ll
  test/CodeGen/X86/vec_minmax_sint.ll
  test/CodeGen/X86/vec_minmax_uint.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-sext-widen.ll
  test/CodeGen/X86/vector-sext.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll
  test/CodeGen/X86/vector-shift-ashr-sub128.ll
  test/CodeGen/X86/vector-shift-lshr-sub128.ll
  test/CodeGen/X86/vector-shift-shl-sub128.ll
  test/CodeGen/X86/vector-trunc-math-widen.ll
  test/CodeGen/X86/vector-trunc-math.ll
  test/CodeGen/X86/vector-trunc-packus-widen.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat-widen.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-trunc-usat-widen.ll
  test/CodeGen/X86/vector-trunc-usat.ll
  test/CodeGen/X86/vselect.ll
  test/CodeGen/X86/xor.ll
  test/CodeGen/X86/zext-logicop-shift-load.ll

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