[llvm] r352294 - AMDGPU/GlobalISel: Widen small uaddo/usubo
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 26 15:44:51 PST 2019
Author: arsenm
Date: Sat Jan 26 15:44:51 2019
New Revision: 352294
URL: http://llvm.org/viewvc/llvm-project?rev=352294&view=rev
Log:
AMDGPU/GlobalISel: Widen small uaddo/usubo
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=352294&r1=352293&r2=352294&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Sat Jan 26 15:44:51 2019
@@ -103,7 +103,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
- .legalFor({{S32, S1}});
+ .legalFor({{S32, S1}})
+ .clampScalar(0, S32, S32);
getActionDefinitionsBuilder(G_BITCAST)
.legalForCartesianProduct({S32, V2S16})
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir?rev=352294&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir Sat Jan 26 15:44:51 2019
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_uaddo_s32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_uaddo_s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO1]](s1)
+ ; CHECK: $vgpr0 = COPY [[UADDO]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32), %3:_(s1) = G_UADDO %0, %1
+ %4:_(s32) = G_ZEXT %3
+ $vgpr0 = COPY %2
+ $vgpr1 = COPY %4
+...
+
+---
+name: test_uaddo_s7
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_uaddo_s7
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: $vgpr0 = COPY [[AND3]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s7) = G_TRUNC %0
+ %3:_(s7) = G_TRUNC %1
+
+ %4:_(s7), %5:_(s1) = G_UADDO %2, %3
+ %6:_(s32) = G_ZEXT %4
+ %7:_(s32) = G_ZEXT %5
+ $vgpr0 = COPY %6
+ $vgpr1 = COPY %7
+...
+
+---
+name: test_uaddo_s16
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_uaddo_s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: $vgpr0 = COPY [[AND3]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+
+ %4:_(s16), %5:_(s1) = G_UADDO %2, %3
+ %6:_(s32) = G_ZEXT %4
+ %7:_(s32) = G_ZEXT %5
+ $vgpr0 = COPY %6
+ $vgpr1 = COPY %7
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir?rev=352294&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir Sat Jan 26 15:44:51 2019
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_usubo_s32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_usubo_s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBO1]](s1)
+ ; CHECK: $vgpr0 = COPY [[USUBO]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32), %3:_(s1) = G_USUBO %0, %1
+ %4:_(s32) = G_ZEXT %3
+ $vgpr0 = COPY %2
+ $vgpr1 = COPY %4
+...
+
+---
+name: test_usubo_s7
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_usubo_s7
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: $vgpr0 = COPY [[AND3]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s7) = G_TRUNC %0
+ %3:_(s7) = G_TRUNC %1
+
+ %4:_(s7), %5:_(s1) = G_USUBO %2, %3
+ %6:_(s32) = G_ZEXT %4
+ %7:_(s32) = G_ZEXT %5
+ $vgpr0 = COPY %6
+ $vgpr1 = COPY %7
+...
+
+---
+name: test_usubo_s16
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_usubo_s16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+ ; CHECK: $vgpr0 = COPY [[AND3]](s32)
+ ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+
+ %4:_(s16), %5:_(s1) = G_USUBO %2, %3
+ %6:_(s32) = G_ZEXT %4
+ %7:_(s32) = G_ZEXT %5
+ $vgpr0 = COPY %6
+ $vgpr1 = COPY %7
+...
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