[llvm] r352283 - [X86][SSE] Generalized unsigned compares to support nonsplat constant vectors (PR39859)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 26 08:40:04 PST 2019
Author: rksimon
Date: Sat Jan 26 08:40:03 2019
New Revision: 352283
URL: http://llvm.org/viewvc/llvm-project?rev=352283&view=rev
Log:
[X86][SSE] Generalized unsigned compares to support nonsplat constant vectors (PR39859)
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/sat-add.ll
llvm/trunk/test/CodeGen/X86/vec_setcc-2.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=352283&r1=352282&r2=352283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jan 26 08:40:03 2019
@@ -19604,17 +19604,20 @@ static SDValue LowerVSETCC(SDValue Op, c
TLI.isOperationLegal(ISD::UMIN, VT)) {
// If we have a constant operand, increment/decrement it and change the
// condition to avoid an invert.
- // TODO: This could be extended to handle a non-splat constant by checking
- // that each element of the constant is not the max/null value.
- APInt C;
- if (Cond == ISD::SETUGT && isConstantSplat(Op1, C) && !C.isMaxValue()) {
+ if (Cond == ISD::SETUGT &&
+ ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) {
+ return !C->getAPIntValue().isMaxValue();
+ })) {
// X > C --> X >= (C+1) --> X == umax(X, C+1)
- Op1 = DAG.getConstant(C + 1, dl, VT);
+ Op1 = DAG.getNode(ISD::ADD, dl, VT, Op1, DAG.getConstant(1, dl, VT));
Cond = ISD::SETUGE;
}
- if (Cond == ISD::SETULT && isConstantSplat(Op1, C) && !C.isNullValue()) {
+ if (Cond == ISD::SETULT &&
+ ISD::matchUnaryPredicate(Op1, [](ConstantSDNode *C) {
+ return !C->getAPIntValue().isNullValue();
+ })) {
// X < C --> X <= (C-1) --> X == umin(X, C-1)
- Op1 = DAG.getConstant(C - 1, dl, VT);
+ Op1 = DAG.getNode(ISD::SUB, dl, VT, Op1, DAG.getConstant(1, dl, VT));
Cond = ISD::SETULE;
}
bool Invert = false;
Modified: llvm/trunk/test/CodeGen/X86/sat-add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sat-add.ll?rev=352283&r1=352282&r2=352283&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sat-add.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sat-add.ll Sat Jan 26 08:40:03 2019
@@ -551,11 +551,9 @@ define <4 x i32> @unsigned_sat_constant_
; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46]
; SSE41-NEXT: paddd %xmm0, %xmm1
-; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967252,4294967251,4294967250,4294967249]
-; SSE41-NEXT: pminud %xmm0, %xmm2
+; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967253,4294967252,4294967251,4294967250]
+; SSE41-NEXT: pmaxud %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
-; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: retq
%a = add <4 x i32> %x, <i32 43, i32 44, i32 45, i32 46>
Modified: llvm/trunk/test/CodeGen/X86/vec_setcc-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_setcc-2.ll?rev=352283&r1=352282&r2=352283&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_setcc-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_setcc-2.ll Sat Jan 26 08:40:03 2019
@@ -511,11 +511,9 @@ define <4 x i1> @ugt_v4i32_nonsplat(<4 x
;
; SSE41-LABEL: ugt_v4i32_nonsplat:
; SSE41: ## %bb.0:
-; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967253,4294967254,4294967255,4294967256]
-; SSE41-NEXT: pminud %xmm0, %xmm1
+; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [4294967254,4294967255,4294967256,4294967257]
+; SSE41-NEXT: pmaxud %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
-; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: retq
%cmp = icmp ugt <4 x i32> %x, <i32 -43, i32 -42, i32 -41, i32 -40>
ret <4 x i1> %cmp
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