[PATCH] D57240: [RISCV] Don't incorrectly force relocation for %pcrel_lo

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 183546.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.

Remove irrelevant dependencies.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57240/new/

https://reviews.llvm.org/D57240

Files:
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  test/MC/RISCV/fixups.s


Index: test/MC/RISCV/fixups.s
===================================================================
--- test/MC/RISCV/fixups.s
+++ test/MC/RISCV/fixups.s
@@ -24,6 +24,8 @@
 # CHECK-FIXUP: fixup A - offset: 0, value: %lo(val), kind: fixup_riscv_lo12_s
 # CHECK-INSTR: sw a0, 1656(t1)
 
+# Create a new fragment boundary here.
+.align 0
 1:
 auipc t1, %pcrel_hi(.LBB0)
 # CHECK-FIXUP: fixup A - offset: 0, value: %pcrel_hi(.LBB0), kind: fixup_riscv_pcrel_hi20
Index: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -11,6 +11,7 @@
 
 #include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
@@ -22,6 +23,7 @@
 
 class RISCVAsmBackend : public MCAsmBackend {
   const MCSubtargetInfo &STI;
+  SmallSet<const MCFixup *, 8> ResolvedPCRelHiFixups;
   uint8_t OSABI;
   bool Is64Bit;
   bool ForceRelocs = false;
Index: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -32,10 +32,13 @@
   switch ((unsigned)Fixup.getKind()) {
   default:
     break;
+  case RISCV::fixup_riscv_pcrel_hi20:
+    ResolvedPCRelHiFixups.insert(&Fixup);
+    break;
   case RISCV::fixup_riscv_pcrel_lo12_i:
   case RISCV::fixup_riscv_pcrel_lo12_s:
-    // For pcrel_lo12, force a relocation if the target of the corresponding
-    // pcrel_hi20 is not in the same fragment.
+    // For pcrel_lo12, force a relocation if the corresponding pcrel_hi20 hasn't
+    // already been resolved without a relocation.
     const MCFixup *T = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup();
     if (!T) {
       Asm.getContext().reportError(Fixup.getLoc(),
@@ -48,8 +51,8 @@
       llvm_unreachable("Unexpected fixup kind for pcrel_lo12");
       break;
     case RISCV::fixup_riscv_pcrel_hi20:
-      ShouldForce = T->getValue()->findAssociatedFragment() !=
-                    Fixup.getValue()->findAssociatedFragment();
+      if (ResolvedPCRelHiFixups.count(T) == 0)
+        ShouldForce = true;
       break;
     }
     break;


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