[PATCH] D40387: [X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>

Thu Jan 24 23:27:57 PST 2019

craig.topper added a comment.

In D40387#1369358 <https://reviews.llvm.org/D40387#1369358>, @RKSimon wrote:

> Shouldn't the MMX pextrw/pinsrw ops be under SSE1 not MMX?

Same could also be said for PADDQ and PSUBQ which are in the MMX file but are SSE2. Despite the Intel SDM mistakenly listing PADDQ as MMX.

Weirdly pextrw is missing from MMX-32.s but its in MMX-64.s

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https://reviews.llvm.org/D40387