[llvm] r352155 - GlobalISel: Implement fewerElementsVector for extensions
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 24 18:36:32 PST 2019
Author: arsenm
Date: Thu Jan 24 18:36:32 2019
New Revision: 352155
URL: http://llvm.org/viewvc/llvm-project?rev=352155&view=rev
Log:
GlobalISel: Implement fewerElementsVector for extensions
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h Thu Jan 24 18:36:32 2019
@@ -120,6 +120,9 @@ private:
void extractParts(unsigned Reg, LLT Ty, int NumParts,
SmallVectorImpl<unsigned> &VRegs);
+ LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
+ LLT NarrowTy);
+
LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
MachineRegisterInfo &MRI;
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Jan 24 18:36:32 2019
@@ -1244,6 +1244,55 @@ LegalizerHelper::lower(MachineInstr &MI,
}
LegalizerHelper::LegalizeResult
+LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
+ LLT NarrowTy) {
+ if (TypeIdx != 0)
+ return UnableToLegalize;
+
+ unsigned DstReg = MI.getOperand(0).getReg();
+ unsigned SrcReg = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ LLT SrcTy = MRI.getType(SrcReg);
+
+ LLT NarrowTy0 = NarrowTy;
+ LLT NarrowTy1;
+ unsigned NumParts;
+
+ if (NarrowTy.isScalar()) {
+ NumParts = DstTy.getNumElements();
+ NarrowTy1 = SrcTy.getElementType();
+ } else {
+ // Uneven breakdown not handled.
+ NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
+ if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
+ return UnableToLegalize;
+
+ NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
+ }
+
+ SmallVector<unsigned, 4> SrcRegs, DstRegs;
+ extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
+
+ for (unsigned I = 0; I < NumParts; ++I) {
+ unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
+ MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
+ .addDef(DstReg)
+ .addUse(SrcRegs[I]);
+
+ NewInst->setFlags(MI.getFlags());
+ DstRegs.push_back(DstReg);
+ }
+
+ if (NarrowTy.isVector())
+ MIRBuilder.buildConcatVectors(DstReg, DstRegs);
+ else
+ MIRBuilder.buildBuildVector(DstReg, DstRegs);
+
+ MI.eraseFromParent();
+ return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
LLT NarrowTy) {
// FIXME: Don't know how to handle secondary types yet.
@@ -1377,6 +1426,11 @@ LegalizerHelper::fewerElementsVector(Mac
MI.eraseFromParent();
return Legalized;
}
+ case TargetOpcode::G_ZEXT:
+ case TargetOpcode::G_SEXT:
+ case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_FPEXT:
+ return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Jan 24 18:36:32 2019
@@ -37,6 +37,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
const LLT S16 = LLT::scalar(16);
const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64);
+ const LLT S128 = LLT::scalar(128);
const LLT S256 = LLT::scalar(256);
const LLT S512 = LLT::scalar(512);
@@ -148,7 +149,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{S64, S32}, {S32, S16}})
- .lowerFor({{S64, S16}}); // FIXME: Implement
+ .lowerFor({{S64, S16}}) // FIXME: Implement
+ .scalarize(0);
getActionDefinitionsBuilder(G_FSUB)
// Use actual fsub instruction
@@ -164,7 +166,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S64, S32}, {S32, S16}, {S64, S16},
- {S32, S1}, {S64, S1}, {S16, S1}});
+ {S32, S1}, {S64, S1}, {S16, S1},
+ // FIXME: Hack
+ {S128, S32}})
+ .scalarize(0);
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalFor({{S32, S32}, {S64, S32}});
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir Thu Jan 24 18:36:32 2019
@@ -75,3 +75,107 @@ body: |
%1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
...
+
+---
+name: test_anyext_v2s16_to_v2s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_anyext_v2s16_to_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s32>) = G_ANYEXT %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_anyext_v3s16_to_v3s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_anyext_v3s16_to_v3s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[DEF]](<3 x s32>)
+ %0:_(<3 x s16>) = G_IMPLICIT_DEF
+ %1:_(<3 x s32>) = G_ANYEXT %0
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
+---
+name: test_anyext_v4s16_to_v4s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_anyext_v4s16_to_v4s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<4 x s32>)
+ %0:_(<4 x s16>) = G_IMPLICIT_DEF
+ %1:_(<4 x s32>) = G_ANYEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_anyext_v2s32_to_v2s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_anyext_v2s32_to_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s64>) = G_ANYEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_anyext_v3s32_to_v3s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2
+
+ ; CHECK-LABEL: name: test_anyext_v3s32_to_v3s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
+ ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[UV2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64), [[ANYEXT2]](s64)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
+ %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x s64>) = G_ANYEXT %0
+ S_NOP 0, implicit %1
+
+...
+
+---
+name: test_anyext_v4s32_to_v4s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_anyext_v4s32_to_v4s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
+ ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[UV2]](s32)
+ ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[UV3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64), [[ANYEXT2]](s64), [[ANYEXT3]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x s64>) = G_ANYEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir Thu Jan 24 18:36:32 2019
@@ -189,8 +189,11 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s8>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[DEF]](<2 x s8>)
- ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SEXT]](<2 x s32>), [[C]](s32)
+ ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF]](<2 x s8>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s8)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s8)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
+ ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
@@ -228,8 +231,11 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[DEF]](<2 x s1>)
- ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SEXT]](<2 x s32>), [[C]](s32)
+ ; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
+ ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[C]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
@@ -248,9 +254,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i32 0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[DEF]](<2 x s1>)
- ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
- ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[SEXT]](<2 x s32>), [[SEXT1]](s32)
+ ; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
+ ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
+ ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[SEXT2]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir Thu Jan 24 18:36:32 2019
@@ -19,6 +19,81 @@ body: |
...
---
+name: test_fpext_v2f16_to_v2f32
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: %4:_(s32) = nnan G_FPEXT [[UV]](s16)
+ ; CHECK: %5:_(s32) = nnan G_FPEXT [[UV1]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s32>) = nnan G_FPEXT %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_fpext_v2f16_to_v2f32_w_flags
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32_w_flags
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: %4:_(s32) = nnan G_FPEXT [[UV]](s16)
+ ; CHECK: %5:_(s32) = nnan G_FPEXT [[UV1]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s32>) = nnan G_FPEXT %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_fpext_v3f16_to_v3f32
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_fpext_v3f16_to_v3f32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<3 x s16>)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[FPEXT]](s32), [[FPEXT1]](s32), [[FPEXT2]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ %0:_(<3 x s16>) = G_IMPLICIT_DEF
+ %1:_(<3 x s32>) = G_FPEXT %0
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
+---
+name: test_fpext_v4f16_to_v4f32
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_fpext_v4f16_to_v4f32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
+ ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
+ ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
+ ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[FPEXT]](s32), [[FPEXT1]](s32), [[FPEXT2]](s32), [[FPEXT3]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ %0:_(<4 x s16>) = G_IMPLICIT_DEF
+ %1:_(<4 x s32>) = G_FPEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
name: test_fpext_f32_to_f64
body: |
bb.0:
@@ -32,3 +107,61 @@ body: |
%1:_(s64) = G_FPEXT %0
$vgpr0_vgpr1 = COPY %1
...
+
+---
+name: test_fpext_v2f32_to_v2f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_fpext_v2f32_to_v2f64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[UV]](s32)
+ ; CHECK: [[FPEXT1:%[0-9]+]]:_(s64) = G_FPEXT [[UV1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FPEXT]](s64), [[FPEXT1]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s64>) = G_FPEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_fpext_v3f32_to_v3f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2
+
+ ; CHECK-LABEL: name: test_fpext_v3f32_to_v3f64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[UV]](s32)
+ ; CHECK: [[FPEXT1:%[0-9]+]]:_(s64) = G_FPEXT [[UV1]](s32)
+ ; CHECK: [[FPEXT2:%[0-9]+]]:_(s64) = G_FPEXT [[UV2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[FPEXT]](s64), [[FPEXT1]](s64), [[FPEXT2]](s64)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
+ %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x s64>) = G_FPEXT %0
+ S_NOP 0, implicit %1
+
+...
+
+---
+name: test_fpext_v4f32_to_v4f64
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_fpext_v4f32_to_v4f64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[UV]](s32)
+ ; CHECK: [[FPEXT1:%[0-9]+]]:_(s64) = G_FPEXT [[UV1]](s32)
+ ; CHECK: [[FPEXT2:%[0-9]+]]:_(s64) = G_FPEXT [[UV2]](s32)
+ ; CHECK: [[FPEXT3:%[0-9]+]]:_(s64) = G_FPEXT [[UV3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[FPEXT]](s64), [[FPEXT1]](s64), [[FPEXT2]](s64), [[FPEXT3]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x s64>) = G_FPEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir Thu Jan 24 18:36:32 2019
@@ -74,3 +74,118 @@ body: |
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...
+
+---
+name: test_sext_v2s16_to_v2s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sext_v2s16_to_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s32>) = G_SEXT %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_sext_v3s16_to_v3s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sext_v3s16_to_v3s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<3 x s16>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
+ ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32), [[SEXT2]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ %0:_(<3 x s16>) = G_IMPLICIT_DEF
+ %1:_(<3 x s32>) = G_SEXT %0
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
+---
+name: test_sext_v4s16_to_v4s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sext_v4s16_to_v4s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
+ ; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
+ ; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[UV3]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32), [[SEXT2]](s32), [[SEXT3]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ %0:_(<4 x s16>) = G_IMPLICIT_DEF
+ %1:_(<4 x s32>) = G_SEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_sext_v2s32_to_v2s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sext_v2s32_to_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s64>) = G_SEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_sext_v3s32_to_v3s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2
+
+ ; CHECK-LABEL: name: test_sext_v3s32_to_v3s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
+ ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
+ %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x s64>) = G_SEXT %0
+ S_NOP 0, implicit %1
+
+...
+
+---
+name: test_sext_v4s32_to_v4s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_sext_v4s32_to_v4s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
+ ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
+ ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
+ ; CHECK: [[SEXT3:%[0-9]+]]:_(s64) = G_SEXT [[UV3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64), [[SEXT3]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x s64>) = G_SEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir?rev=352155&r1=352154&r2=352155&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir Thu Jan 24 18:36:32 2019
@@ -79,3 +79,118 @@ body: |
%1:_(s64) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1
...
+
+---
+name: test_zext_v2s16_to_v2s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zext_v2s16_to_v2s32
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s32>) = G_ZEXT %0
+ $vgpr0_vgpr1 = COPY %1
+...
+
+---
+name: test_zext_v3s16_to_v3s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zext_v3s16_to_v3s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<3 x s16>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
+ ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ %0:_(<3 x s16>) = G_IMPLICIT_DEF
+ %1:_(<3 x s32>) = G_ZEXT %0
+ $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
+---
+name: test_zext_v4s16_to_v4s32
+body: |
+ bb.0.entry:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zext_v4s16_to_v4s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
+ ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
+ ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32), [[ZEXT3]](s32)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
+ %0:_(<4 x s16>) = G_IMPLICIT_DEF
+ %1:_(<4 x s32>) = G_ZEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_zext_v2s32_to_v2s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zext_v2s32_to_v2s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x s64>) = G_ZEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
+...
+
+---
+name: test_zext_v3s32_to_v3s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2
+
+ ; CHECK-LABEL: name: test_zext_v3s32_to_v3s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
+ ; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64)
+ ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
+ %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(<3 x s64>) = G_ZEXT %0
+ S_NOP 0, implicit %1
+
+...
+
+---
+name: test_zext_v4s32_to_v4s64
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_zext_v4s32_to_v4s64
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
+ ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
+ ; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
+ ; CHECK: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[UV3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64), [[ZEXT3]](s64)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(<4 x s64>) = G_ZEXT %0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
+...
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