[PATCH] D57163: [DebugInfo][DAG] PR40427: Avoid accidentally re-ordering DBG_VALUEs due to assumptions about inst creation

[Adrian Prantl via Phabricator via llvm-commits]

aprantl added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp:823
+    auto GetPrevInsn = [&](MachineBasicBlock::iterator I) {
+      bool BadPos = BB->begin() == BB->end() || I == BB->begin();
+      if (BadPos)
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if `BB->begin() == BB->end()` doesn't that imply `I == BB->begin()`, too?



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Comment at: lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp:844
+      }
+    } else {
+      // No new instruction.
----------------
early return instead?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57163/new/

https://reviews.llvm.org/D57163