[llvm] r352037 - [MIPS GlobalISel] Combine extending loads
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 24 02:09:52 PST 2019
Author: petar.avramovic
Date: Thu Jan 24 02:09:52 2019
New Revision: 352037
URL: http://llvm.org/viewvc/llvm-project?rev=352037&view=rev
Log:
[MIPS GlobalISel] Combine extending loads
Use CombinerHelper to combine extending load instructions.
G_LOAD combined with G_ZEXT, G_SEXT or G_ANYEXT gives G_ZEXTLOAD,
G_SEXTLOAD or G_LOAD with same type as def of extending instruction
respectively.
Similarly G_ZEXTLOAD combined with G_ZEXT gives G_ZEXTLOAD and
G_SEXTLOAD combined with G_SEXT gives G_SEXTLOAD with same type
as def of extending instruction.
Differential Revision: https://reviews.llvm.org/D56914
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp?rev=352037&r1=352036&r2=352037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsPreLegalizerCombiner.cpp Thu Jan 24 02:09:52 2019
@@ -13,6 +13,7 @@
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
+#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -34,6 +35,16 @@ public:
bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
+ CombinerHelper Helper(Observer, B);
+
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case TargetOpcode::G_LOAD:
+ case TargetOpcode::G_SEXTLOAD:
+ case TargetOpcode::G_ZEXTLOAD:
+ return Helper.tryCombineExtendingLoads(MI);
+ }
return false;
}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir?rev=352037&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir Thu Jan 24 02:09:52 2019
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
+ define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
+
+...
+---
+name: load1_s8_to_load1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_load1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load2_s16_to_load2_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load2_s16_to_load2_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.px)
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir?rev=352037&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir Thu Jan 24 02:09:52 2019
@@ -0,0 +1,188 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
+ define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
+ define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
+ define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
+ define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
+
+...
+---
+name: load1_s8_to_zextLoad1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s32) = G_ZEXT %1(s8)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load2_s16_to_zextLoad2_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
+ ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
+ %2:_(s32) = G_ZEXT %1(s16)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load1_s8_to_zextLoad1_s16
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
+ ; MIPS32: $v0 = COPY [[ANYEXT]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s16) = G_ZEXT %1(s8)
+ %3:_(s32) = G_ANYEXT %2(s16)
+ $v0 = COPY %3(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s16) = G_ZEXT %1(s8)
+ %3:_(s32) = G_ZEXT %2(s16)
+ $v0 = COPY %3(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load1_s8_to_sextLoad1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s32) = G_SEXT %1(s8)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load2_s16_to_sextLoad2_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
+ ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
+ %2:_(s32) = G_SEXT %1(s16)
+ $v0 = COPY %2(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load1_s8_to_sextLoad1_s16
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
+ ; MIPS32: $v0 = COPY [[ANYEXT]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s16) = G_SEXT %1(s8)
+ %3:_(s32) = G_ANYEXT %2(s16)
+ $v0 = COPY %3(s32)
+ RetRA implicit $v0
+
+...
+---
+name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
+ ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
+ ; MIPS32: RetRA implicit $v0
+ %0:_(p0) = COPY $a0
+ %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
+ %2:_(s16) = G_SEXT %1(s8)
+ %3:_(s32) = G_SEXT %2(s16)
+ $v0 = COPY %3(s32)
+ RetRA implicit $v0
+
+...
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