[PATCH] D54583: PowerPC: Optimize SPE double parameter calling setup

[Kei Thomsen via Phabricator via llvm-commits]

kthomsen added a comment.

As promised I have modified the SelectAddressRegReg() in PPCISelLowering.cpp to create correct evldd(x) and evstdd(x) instructions when accessing global variables.

bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,

                                            SDValue &Index,
                                            SelectionDAG &DAG) const {
  int16_t imm = 0;
  if (N.getOpcode() == ISD::ADD) {
    if (hasSPE()) {
      // Is there any SPE load/store (f64) which can't handle 16bit offset?
      for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
          UI != E; ++UI) {
        if (UI->getOpcode() == ISD::STORE) {
          // Store has the type Operand[1]
          if ((UI->getNumOperands() >= 2) 
            && (UI->getOperand(1).getSimpleValueType() == MVT::f64)) {
              // This is a f64 store with SPE
              // The instruction evstdd can only handle 8bit offset
              Base = N.getOperand(0);
              Index = N.getOperand(1);
              return true;
          }
        } else
        if (UI->getOpcode() == ISD::LOAD) {
          // Load has the type in Values[0]
          if ((UI->getNumValues() >= 1) 
            && (UI->getSimpleValueType(0) == MVT::f64)) {
              // This is a f64 load with SPE
              // The instruction evldd can only handle 8bit offset
              Base = N.getOperand(0);
              Index = N.getOperand(1);
              return true;
          }
        }
      }
    }
    if (isIntS16Immediate(N.getOperand(1), imm))
      return false;    // r+i
    if (N.getOperand(1).getOpcode() == PPCISD::Lo)
      return false;    // r+i

....
The modification starts with if(hasSPE()) { and ends with the fitting }

What have I done: The SelectAddressRegReg() function is the central decider for "offset+r4" or "r4+r5", but it only knows about 16bit offsets. evldd and evstdd are using 8bit (5bit usable) offsets. Therefore they can't be used when accessing global variables. The patch in here is now looking in the useList if it is a SPE with Load or Store for f64 data. Then it tells, that it must be Register+Register addressing, which is then automatically chaning to evlddx / evstddx.
I have tested this with OS-9 running on a P2020 <https://reviews.llvm.org/P2020> (e500v2).

Would you like to put my patch into your patch D54583 <https://reviews.llvm.org/D54583>?
Kei


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https://reviews.llvm.org/D54583