[PATCH] D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: efriedma, rogfer01.
Herald added subscribers: jocewei, PkmX, jfb, rkruppe, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.

The previous DAG combiner-based approach had an issue with infinite loops between the target-dependent and target-independent combiner logic (see PR40333 <https://bugs.llvm.org/show_bug.cgi?id=40333>). Although this was worked around in rL351806 <https://reviews.llvm.org/rL351806>, the combiner-based approach is still potentially brittle and can fail to select the 32-bit shift variant when profitable to do so, as demonstrated in the pr40333.ll test case.

This patch instead introduces target-specific SelectionDAG nodes for SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a good example of how this approach can improve codegen.

There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new instruction sequences are semantically equivalent.

It likely makes sense to replace the 32-bit sdiv/udiv/srem combining logic in a similar way, but that belongs in a separate patch.


https://reviews.llvm.org/D57085

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/atomic-cmpxchg.ll
  test/CodeGen/RISCV/atomic-rmw.ll
  test/CodeGen/RISCV/pr40333.ll

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