[PATCH] D52922: AMDGPU/GlobalISel: Move SMRD selection logic to TableGen

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:645
+  unsigned PtrReg = GEPInfo.SgprParts[0];
+  unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
+  BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
----------------
_XM0


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Comment at: test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir:90
 
+# Ponter loads
+# GCN: [[AS0:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0
----------------
Pointer


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Comment at: test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir:149
 
+    %28:sgpr(p0) = G_LOAD %0 :: (load 8 from %ir.const0)
+    $sgpr0_sgpr1 = COPY %28
----------------
address space missing from all the MMOs


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52922/new/

https://reviews.llvm.org/D52922