[PATCH] D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

@craig.topper Should any Intel model account for this in a similar way? Agner is a little vague on this.



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Comment at: lib/Target/X86/X86Schedule.td:20
 
+def ReadInt2Fpu : SchedRead;
+
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